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1. 发明授权

US06828254B2 Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same 失效
标题翻译：等离子体增强化学气相沉积装置和使用其形成氮化物层的方法
公开(公告)号：US06828254B2
公开(公告)日：2004-12-07
申请号：US10277801
申请日：2002-10-23
申请人： Jae-Jong Han , Kyoung-Seok Kim , Byung-Ho Ahn , Seung Mok Shin , Hwa-Sik Kim , Hong-Bae Park
发明人： Jae-Jong Han , Kyoung-Seok Kim , Byung-Ho Ahn , Seung Mok Shin , Hwa-Sik Kim , Hong-Bae Park
IPC分类号： H01L2131
CPC分类号： C23C16/4558 , C23C16/345 , C23C16/4404 , C23C16/4405 , C23C16/505 , H01J37/3244 , H01J37/32623
摘要： A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.
摘要翻译：一种等离子体增强化学气相沉积装置和使用其形成氮化物层的方法，其中等离子体增强CVD装置包括处理室，该处理室包括具有圆顶形状的上室，下室和位于其间的绝缘体，气体分布环，用于支撑晶片并加热处理室的基座，围绕基座的等离子体补偿环，真空泵和连接到处理室的电源。气体分配环具有多个向上倾斜的喷嘴，允许反应气体向上分配。形成氮化物层的方法包括在处理室的内壁上形成保护膜，所述保护膜具有至少两层不同的介电常数，并且将反应性气体顺序地供应到处理室。由此形成的氮化物层具有低氢含量，良好的密度和抗氧化性。

2. 发明授权

US06815370B2 Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same 失效
标题翻译：等离子体增强化学气相沉积装置和使用其形成氮化物层的方法
公开(公告)号：US06815370B2
公开(公告)日：2004-11-09
申请号：US10805335
申请日：2004-03-22
申请人： Jae-Jong Han , Kyoung-Seok Kim , Byung-Ho Ahn , Seung Mok Shin , Hwa-Sik Kim , Hong-Bae Park
发明人： Jae-Jong Han , Kyoung-Seok Kim , Byung-Ho Ahn , Seung Mok Shin , Hwa-Sik Kim , Hong-Bae Park
IPC分类号： H01L2131
CPC分类号： C23C16/4558 , C23C16/345 , C23C16/4404 , C23C16/4405 , C23C16/505 , H01J37/3244 , H01J37/32623
摘要： A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

3. 发明授权

US06794263B1 Method of manufacturing a semiconductor device including alignment mark 有权
标题翻译：制造包括对准标记的半导体器件的方法
公开(公告)号：US06794263B1
公开(公告)日：2004-09-21
申请号：US10367931
申请日：2003-02-19
申请人： Kong-Soo Lee , Young-Wook Park , Jae-Jong Han , Gi-Hyun Hwang , Kyoung-Seok Kim , Sung-Eui Kim , Seung-Mok Shin
发明人： Kong-Soo Lee , Young-Wook Park , Jae-Jong Han , Gi-Hyun Hwang , Kyoung-Seok Kim , Sung-Eui Kim , Seung-Mok Shin
IPC分类号： H01L2176
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/76229 , H01L2223/54453 , H01L2924/0002 , Y10S438/959 , Y10S438/975 , H01L2924/00
摘要： A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.
摘要翻译：在半导体器件的制造期间抑制半导体衬底上的凹坑产生的方法包括在半导体衬底中形成使用浅沟槽隔离（STI）方法的隔离，在具有隔离的半导体衬底的整个表面上形成绝缘层，使用绝缘层作为缓冲层将离子注入到半导体衬底中，使用快速热退火（RTA）工艺对半导体衬底进行退火，在绝缘层上形成光致抗蚀剂层，然后在光刻胶层中形成开口以暴露底层通过在开口处蚀刻底层形成对准键，以及去除光致抗蚀剂层和绝缘层。或者，可以减小绝缘层的厚度，以防止在半导体衬底的有源区域上出现凹坑。

4. 发明授权

US06730570B2 Method for forming a self-aligned contact of a semiconductor device and method for manufacturing a semiconductor device using the same 有权
标题翻译：用于形成半导体器件的自对准接触的方法和使用其制造半导体器件的方法
公开(公告)号：US06730570B2
公开(公告)日：2004-05-04
申请号：US10348017
申请日：2003-01-22
申请人： Seung-Mok Shin , Jae-Jong Han , Ki-Hyun Hwang
发明人： Seung-Mok Shin , Jae-Jong Han , Ki-Hyun Hwang
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76831 , H01L29/6656
摘要： A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.
摘要翻译：提供了一种用于在可以减少工艺故障的半导体器件中形成自对准接触的方法以及包括自对准接触的半导体器件的制造方法。在层间电介质膜中形成自对准接触孔，以在其上形成的导电结构之间露出基板的一部分。在自对准接触孔的侧壁，自对准接触孔的底部和层间电介质膜上形成缓冲层，使得缓冲层在自对准的上部的厚度接触孔大于自对准接触孔底部缓冲层的厚度。在自对准接触孔的底部上移除缓冲层的部分之后，在自对准接触孔中形成接触以与衬底接触。

5. 发明授权

US06881637B2 Method of forming a gate electrode, method of manufacturing a semiconductor device having the gate electrode, and method of oxidizing a substrate 有权
标题翻译：形成栅电极的方法，制造具有栅电极的半导体器件的方法以及氧化衬底的方法
公开(公告)号：US06881637B2
公开(公告)日：2005-04-19
申请号：US10672884
申请日：2003-09-26
申请人： Jae-Jong Han , Yong-Woo Hyung , Seung-Mok Shin , Kong-Soo Lee , Eun-Jung Yun
发明人： Jae-Jong Han , Yong-Woo Hyung , Seung-Mok Shin , Kong-Soo Lee , Eun-Jung Yun
IPC分类号： H01L21/336 , H01L21/28 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/28247 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.
摘要翻译：在形成具有优异的侧壁轮廓的栅电极的方法中，在基板上形成栅极结构之后，在栅极结构的侧壁和基板上形成第一氧化膜，通过重新氧化栅极结构和在包含氧气和惰性气体的气氛下进行。栅极结构具有栅极氧化膜图案，多晶硅膜图案和金属硅化物膜图案。形成在多晶硅膜图案的侧壁上的第一氧化膜的一部分的厚度与形成在金属硅化物膜图案的侧壁上的第一氧化物膜的部分的厚度基本相同。具有栅电极的半导体器件的故障可以最小化，因为栅电极具有改进的侧壁轮廓。

6. 发明申请

US20100323489A1 Method of forming a vertical diode and method of manufacturing a semiconductor device using the same 有权
公开(公告)号：US20100323489A1
公开(公告)日：2010-12-23
申请号：US12805825
申请日：2010-08-20
申请人： Sang-Jin Park , Kong-Soo Lee , Yong-Woo Hyung , Young-Sub You , Jae-Jong Han
发明人： Sang-Jin Park , Kong-Soo Lee , Yong-Woo Hyung , Young-Sub You , Jae-Jong Han
IPC分类号： H01L21/02
CPC分类号： H01L45/143 , H01L21/0237 , H01L21/02488 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L27/1021 , H01L27/2409 , H01L29/66136 , H01L29/66204 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

7. 发明授权

US07118975B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07118975B2
公开(公告)日：2006-10-10
申请号：US10872360
申请日：2004-06-22
申请人： Jae-Jong Han , Young-Wook Park , Jae-Hyun Yeo
发明人： Jae-Jong Han , Young-Wook Park , Jae-Hyun Yeo
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/76235 , H01L21/823481 , H01L27/105 , H01L27/1052 , H01L27/10876
摘要： Provided is a method for manufacturing semiconductor devices including channel trenches that are separated by isolation structures. According to the process, the substrate is etched to form isolation trenches after which a sidewall oxide layer, a liner nitride layer and a field oxide layer are subsequently formed on the substrate and in the isolation trenches. The substrate is then planarized to remove upper portions of the sidewall oxide layer, the liner nitride layer and the field oxide layer to expose surface portions of the substrate between adjacent isolation trench structures. Channel trenches are then formed in the exposed surface portions of the substrate leaving residual substrate regions adjacent the isolation trench structures. These residual substrate regions are then oxidized and removed to form improved second channel trenches for the formation of transistor regions.
摘要翻译：提供一种半导体器件的制造方法，其包括由隔离结构分离的沟槽。根据该过程，蚀刻衬底以形成隔离沟槽，之后随后在衬底和隔离沟槽中形成侧壁氧化物层，衬里氮化物层和场氧化物层。然后将衬底平坦化以除去侧壁氧化物层，衬里氮化物层和场氧化物层的上部，以暴露在相邻的隔离沟槽结构之间的衬底的表面部分。然后在衬底的暴露的表面部分中形成通道沟槽，留下邻近隔离沟槽结构的残余衬底区域。然后将这些残留的衬底区域氧化并除去以形成用于形成晶体管区域的改进的第二沟道沟槽。

8. 发明申请

US20050233559A1 Method of forming a layer on a wafer 失效
标题翻译：在晶片上形成层的方法
公开(公告)号：US20050233559A1
公开(公告)日：2005-10-20
申请号：US11061407
申请日：2005-02-18
申请人： Ji-Sang Yahng , Young-Wook Park , Jae-Jong Han , Jum-Soo Chang
发明人： Ji-Sang Yahng , Young-Wook Park , Jae-Jong Han , Jum-Soo Chang
IPC分类号： H01L21/31 , H01L21/00 , H01L21/20 , H01L21/205 , H01L21/316
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/67109 , H01L21/67757 , Y10S414/136 , Y10S414/139
摘要： A layer is formed on a semiconductor wafer in an apparatus having a processing chamber, a transferring chamber, and a wafer boat. The boat having the semiconductor wafer thereon is rotated in the transferring chamber. While the boat is rotated, the boat is transferred between the transferring chamber and the processing chamber and a reaction gas is provided to the processing chamber to form the layer on the wafer.
摘要翻译：在具有处理室，转印室和晶片舟皿的装置中的半导体晶片上形成层。其上具有半导体晶片的船在转印室中旋转。当船旋转时，船在转移室和处理室之间转移，并且反应气体被提供到处理室以在晶片上形成层。

9. 发明授权

US06225199B1 Semiconductor device having triple-well 有权
标题翻译：具有三重阱的半导体器件
公开(公告)号：US06225199B1
公开(公告)日：2001-05-01
申请号：US09348381
申请日：1999-07-07
申请人： Jae-Jong Han , Doo-Hyun Hwang , Byung-Kee Kim , Beung-Keun Lee
发明人： Jae-Jong Han , Doo-Hyun Hwang , Byung-Kee Kim , Beung-Keun Lee
IPC分类号： H01L21265
CPC分类号： H01L21/761 , H01L27/10894
摘要： The triple-well according to the present invention reduces a photo process forming a well isolation region which is used in a method for forming a prior well. That is, two times of photo processes are reduced to be one time, thereby simplifying a method for forming a triple-well of the DRAM device and reducing time and expenditure.
摘要翻译：根据本发明的三重阱减少了形成井分离区域的光刻工艺，其用于形成先前井的方法。也就是说，将两次照相处理减少为一次，从而简化了用于形成DRAM器件的三阱的方法并减少了时间和费用。

10. 发明申请

US20160293705A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160293705A1
公开(公告)日：2016-10-06
申请号：US14977865
申请日：2015-12-22
申请人： Han-ki Lee , Jae-Young Park , Dong-Hun Lee , Bon-Young Koo , Sun-Young Lee , Jae-Jong Han
发明人： Han-ki Lee , Jae-Young Park , Dong-Hun Lee , Bon-Young Koo , Sun-Young Lee , Jae-Jong Han
IPC分类号： H01L29/10 , H01L29/786 , H01L29/423 , H01L29/78
CPC分类号： H01L29/1054 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括包括锗和内部区域以及外部区域的多通道活性图案，沿着内部区域的轮廓形成外部区域，并且外部区域的锗部分小于内部区域的锗部分地区。栅电极与多通道有源图案相交。

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