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1. 发明授权

US06730570B2 Method for forming a self-aligned contact of a semiconductor device and method for manufacturing a semiconductor device using the same 有权
标题翻译：用于形成半导体器件的自对准接触的方法和使用其制造半导体器件的方法
公开(公告)号：US06730570B2
公开(公告)日：2004-05-04
申请号：US10348017
申请日：2003-01-22
申请人： Seung-Mok Shin , Jae-Jong Han , Ki-Hyun Hwang
发明人： Seung-Mok Shin , Jae-Jong Han , Ki-Hyun Hwang
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76831 , H01L29/6656
摘要： A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.
摘要翻译：提供了一种用于在可以减少工艺故障的半导体器件中形成自对准接触的方法以及包括自对准接触的半导体器件的制造方法。在层间电介质膜中形成自对准接触孔，以在其上形成的导电结构之间露出基板的一部分。在自对准接触孔的侧壁，自对准接触孔的底部和层间电介质膜上形成缓冲层，使得缓冲层在自对准的上部的厚度接触孔大于自对准接触孔底部缓冲层的厚度。在自对准接触孔的底部上移除缓冲层的部分之后，在自对准接触孔中形成接触以与衬底接触。

2. 发明授权

US09240357B2 Method of fabricating semiconductor device having preliminary stacked structure with offset oxide etched using gas cluster ion 有权
标题翻译：制造半导体器件的方法，该半导体器件具有使用气体簇离子蚀刻的具有偏移氧化物的初步堆叠
公开(公告)号：US09240357B2
公开(公告)日：2016-01-19
申请号：US14100651
申请日：2013-12-09
申请人： Tae-Gon Kim , Jong-Hoon Kang , Jae-Young Ahn , Jun-Kyu Yang , Han-Mei Choi , Ki-Hyun Hwang
发明人： Tae-Gon Kim , Jong-Hoon Kang , Jae-Young Ahn , Jun-Kyu Yang , Han-Mei Choi , Ki-Hyun Hwang
IPC分类号： H01L21/66 , H01L21/265 , H01L21/311 , H01L27/115
CPC分类号： H01L22/12 , H01L21/31116 , H01L22/20 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.
摘要翻译：根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

3. 发明授权

US09082659B1 Methods of forming vertical type semiconductor devices including oxidation target layers 有权
标题翻译：形成包括氧化靶层的垂直型半导体器件的方法
公开(公告)号：US09082659B1
公开(公告)日：2015-07-14
申请号：US14643527
申请日：2015-03-10
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

4. 发明授权

US09064736B2 Method of manufacturing three dimensional semiconductor memory device 有权
标题翻译：制造三维半导体存储器件的方法
公开(公告)号：US09064736B2
公开(公告)日：2015-06-23
申请号：US14248003
申请日：2014-04-08
申请人： Joon-Suk Lee , Woong Lee , Hun-Hyeong Lim , Ki-Hyun Hwang
发明人： Joon-Suk Lee , Woong Lee , Hun-Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L21/311 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film. Forming the lower epitaxial film, doping the impurity into the lower epitaxial film and forming the upper epitaxial film are all performed in-situ, and the semiconductor pattern includes a doped region and an undoped region.
摘要翻译：提供一种制造三维半导体存储器件的方法。该方法包括在基板上交替堆叠第一绝缘膜，第一牺牲膜，交替的第二绝缘膜和第二牺牲膜，第三牺牲膜和第三绝缘膜。形成通道孔，以在穿过第一绝缘膜，第一牺牲膜，第二绝缘膜，第二牺牲膜，第三牺牲膜和第三绝缘膜的同时暴露衬底的一部分。该方法还包括通过外延生长在暴露在通道孔中的衬底的部分上形成半导体图案。形成半导体图案包括形成下部外延膜，将杂质掺杂到下部外延膜中，以及在下部外延膜上形成上部外延膜。形成下部外延膜，将杂质掺杂到下部外延膜中并形成上部外延膜全部原位进行，并且半导体图案包括掺杂区域和未掺杂区域。

5. 发明申请

US20140084357A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140084357A1
公开(公告)日：2014-03-27
申请号：US13949447
申请日：2013-07-24
申请人： Ji-Hoon Choi , Dong-Kyum Kim , Jin-Gyun Kim , Su-Jin Shin , Sang-Hoon Lee , Ki-Hyun Hwang
发明人： Ji-Hoon Choi , Dong-Kyum Kim , Jin-Gyun Kim , Su-Jin Shin , Sang-Hoon Lee , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02236 , H01L21/02252 , H01L21/02255 , H01L21/28008 , H01L21/28282 , H01L27/1157 , H01L29/7926
摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.
摘要翻译：提供半导体器件。半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅极电极。多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。栅电介质层设置在侧表面上。沟道图案设置在栅介质层上。栅介质层包括保护图案，电荷陷阱层和隧穿层。保护图案包括设置在多个栅电极的对应的栅电极上的部分。电荷陷阱层设置在保护图案上。隧道层设置在电荷陷阱层和沟道图案之间。保护图案比电荷陷阱层更致密。

6. 发明申请

US20110165750A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES 审中-公开
标题翻译：制造包括结构在内的半导体器件的方法
公开(公告)号：US20110165750A1
公开(公告)日：2011-07-07
申请号：US12984940
申请日：2011-01-05
申请人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Chan-Jin Park
发明人： Jun-Kyu Yang , Young-Geun Park , Ki-Hyun Hwang , Han-Mei Choi , Chan-Jin Park
IPC分类号： H01L21/336
CPC分类号： H01L21/7682 , H01L21/02164 , H01L21/02266 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.
摘要翻译：在制造半导体器件的方法中，多个彼此间隔开的栅极结构和氧化物层图案。执行使用氧化物层图案作为溅射靶的溅射工艺来将相邻栅极结构上的氧化物层图案彼此连接，使得在栅极结构之间形成间隙。通过控制氧化物层图案的厚度，使间隙的体积均匀地形成为具有期望的体积。

7. 发明申请

US20110045667A1 Gate of a transistor and method of forming the same 审中-公开
标题翻译：晶体管的栅极及其形成方法
公开(公告)号：US20110045667A1
公开(公告)日：2011-02-24
申请号：US12926151
申请日：2010-10-28
申请人： Jin-Gyun Kim , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Jin-Gyun Kim , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823456 , H01L21/82385
摘要： A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.
摘要翻译：晶体管的栅极包括形成在半导体器件上的栅极氧化层，包含掺杂有硼的多晶硅并形成在栅极氧化物层上的第一导电层图案，包括通过化学气相沉积工艺形成的非晶硅的扩散防止层图案，其使用形成在第一导电层图案上的具有丙硅烷（Si 3 H 8）的反应气体和形成在扩散防止层图案上的包含金属硅化物的第二导电层图案。由于PMOS晶体管的栅极包括具有优异表面形态的扩散防止层，因此充分防止了杂质的扩散。因此，可以降低PMOS晶体管的阈值电压，并且可以提高阈值电压分布。

8. 发明授权

US07846836B2 Method of forming a conductive structure in a semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：在半导体器件中形成导电结构的方法和制造半导体器件的方法
公开(公告)号：US07846836B2
公开(公告)日：2010-12-07
申请号：US12453231
申请日：2009-05-04
申请人： Dong-Kak Lee , Ki-Hyun Hwang , Jin-Gyun Kim
发明人： Dong-Kak Lee , Ki-Hyun Hwang , Jin-Gyun Kim
IPC分类号： H01L21/44
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76829 , H01L29/6656 , H01L29/6659 , H01L29/66621
摘要： A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.
摘要翻译：在半导体器件中形成导电结构的方法包括在衬底上形成导电层，在衬底上形成导电层图案，通过图案化导电层，在衬底上形成氧化物层和导电层的一部分，以及在氧化物层和导电层图案上形成覆盖层。

9. 发明申请

US20090134451A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090134451A1
公开(公告)日：2009-05-28
申请号：US12292543
申请日：2008-11-20
申请人： Seung-Jae Baik , Jin-Tae Noh , Hong-Suk Kim , In-Sun Yi , Si-Young Choi , Ki-Hyun Hwang
发明人： Seung-Jae Baik , Jin-Tae Noh , Hong-Suk Kim , In-Sun Yi , Si-Young Choi , Ki-Hyun Hwang
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , B82Y10/00 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/792
摘要： An example embodiment of a non-volatile memory device and an example embodiment of a method of fabricating the same are provided. The non-volatile memory devices includes a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a blocking insulation layer including at least one nano dot on the charge storage layer, and a control gate electrode on the blocking insulation layer.
摘要翻译：提供非易失性存储器件的示例性实施例及其制造方法的示例性实施例。非易失性存储器件包括在半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，在电荷存储层上包括至少一个纳米点的阻挡绝缘层，以及阻挡层上的控制栅电极绝缘层。

10. 发明申请

US20090045448A1 Non-volatile memory device and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090045448A1
公开(公告)日：2009-02-19
申请号：US12222568
申请日：2008-08-12
申请人： Seung-Jae Baik , Si-Young Choi , Ki-Hyun Hwang
发明人： Seung-Jae Baik , Si-Young Choi , Ki-Hyun Hwang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42348 , H01L29/42352
摘要： Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines.
摘要翻译：示例性实施例提供非易失性存储器件及其形成方法。非易失性存储器件可以在半导体衬底中限定有源区，并且可以包括沿第一方向延伸的器件隔离层，半导体衬底中的位线，沿与第一方向相交的第二方向延伸的位线; 字线在第一方向上延伸并覆盖有源区; 并且对字线和有源区域之间的存储模式进行充电，其中电荷存储模式可以在位线的两个边缘上成对配对，并且一对电荷存储模式可以通过字线彼此间隔开。

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