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1. 发明授权

US06914316B2 Semiconductor trench isolation structure 有权
标题翻译：半导体沟槽隔离结构
公开(公告)号：US06914316B2
公开(公告)日：2005-07-05
申请号：US10617742
申请日：2003-07-14
申请人： Eun-Jung Yun , Sung-Eui Kim
发明人： Eun-Jung Yun , Sung-Eui Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L29/00
CPC分类号： H01L21/76229
摘要： A trench structure of a semiconductor device includes first and second regions of a substrate having first and second trenches, respectively, the first trench having an aspect ratio larger than that of the second trench, a first insulation material on a bottom and sidewalls of the first trench forming a first sub-trench in the first trench, a second insulation material completely filling the first sub-trench, a third insulation material formed on a bottom and sidewalls of the second trench forming a second sub-trench in the second trench, a fourth insulation material formed on a bottom and sidewalls of the second sub-trench, and a fifth insulation material completely filling a third sub-trench formed in the second sub-trench by the fourth insulation material.
摘要翻译：半导体器件的沟槽结构包括分别具有第一和第二沟槽的衬底的第一和第二区域，第一沟槽的纵横比分别大于第二沟槽的纵横比，第一绝缘材料位于第一和第二沟槽的底部和侧壁上在所述第一沟槽中形成第一子沟槽的沟槽，完全填充所述第一子沟槽的第二绝缘材料，形成在所述第二沟槽的底部和侧壁上的第三绝缘材料，所述第二沟槽在所述第二沟槽中形成第二子沟槽，第四绝缘材料形成在第二子沟槽的底部和侧壁上，第五绝缘材料通过第四绝缘材料完全填充形成在第二子沟槽中的第三子沟槽。

2. 发明授权

US06794263B1 Method of manufacturing a semiconductor device including alignment mark 有权
标题翻译：制造包括对准标记的半导体器件的方法
公开(公告)号：US06794263B1
公开(公告)日：2004-09-21
申请号：US10367931
申请日：2003-02-19
申请人： Kong-Soo Lee , Young-Wook Park , Jae-Jong Han , Gi-Hyun Hwang , Kyoung-Seok Kim , Sung-Eui Kim , Seung-Mok Shin
发明人： Kong-Soo Lee , Young-Wook Park , Jae-Jong Han , Gi-Hyun Hwang , Kyoung-Seok Kim , Sung-Eui Kim , Seung-Mok Shin
IPC分类号： H01L2176
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/76229 , H01L2223/54453 , H01L2924/0002 , Y10S438/959 , Y10S438/975 , H01L2924/00
摘要： A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.
摘要翻译：在半导体器件的制造期间抑制半导体衬底上的凹坑产生的方法包括在半导体衬底中形成使用浅沟槽隔离（STI）方法的隔离，在具有隔离的半导体衬底的整个表面上形成绝缘层，使用绝缘层作为缓冲层将离子注入到半导体衬底中，使用快速热退火（RTA）工艺对半导体衬底进行退火，在绝缘层上形成光致抗蚀剂层，然后在光刻胶层中形成开口以暴露底层通过在开口处蚀刻底层形成对准键，以及去除光致抗蚀剂层和绝缘层。或者，可以减小绝缘层的厚度，以防止在半导体衬底的有源区域上出现凹坑。

3. 发明授权

US06461937B1 Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法
公开(公告)号：US06461937B1
公开(公告)日：2002-10-08
申请号：US09479442
申请日：2000-01-07
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

4. 发明授权

US6093622A Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) 失效
标题翻译：使用通过化学气相沉积（CVD）形成的第二衬垫氧化物层的半导体器件的隔离方法
公开(公告)号：US6093622A
公开(公告)日：2000-07-25
申请号：US148060
申请日：1998-09-04
申请人： Dong-ho Ahn , Sung-eui Kim , Yu-gyun Shin
发明人： Dong-ho Ahn , Sung-eui Kim , Yu-gyun Shin
IPC分类号： H01L21/285 , H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.
摘要翻译：提供了半导体器件的制造工艺中的隔离方法。该方法形成通过化学气相沉积（CVD）来减少应力的缓冲层的氧化物层。通过该方法，在半导体衬底上形成第一衬垫氧化物层和氮化硅层，然后通过图案形成氮化硅层图案，并且在第一衬垫氧化物层图案中形成底切。随后，通过CVD在半导体衬底的整个表面上形成第二焊盘氧化物层，然后在图案化的第一焊盘氧化物层和氮化硅层的侧壁上形成间隔物，并且通过热氧化形成场氧化物层。或者，沉积硅层而没有间隔物以形成场氧化物层。第二衬垫氧化物层是用于在形成场氧化物层期间缓冲应力的缓冲层。

5. 发明授权

US5824594A Integrated circuit device isolating methods including silicon spacers and oxidation barrier films 失效
标题翻译：集成电路器件隔离方法，包括硅隔离层和氧化阻挡膜
公开(公告)号：US5824594A
公开(公告)日：1998-10-20
申请号：US837208
申请日：1997-04-14
申请人： Sung-eui Kim , Young-dae Kim
发明人： Sung-eui Kim , Young-dae Kim
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76205
摘要： An integrated circuit device is isolated by forming a pad oxide layer on an integrated circuit substrate. A mask pattern is formed on the pad layer. The mask pattern includes sidewalls which selectively expose the pad oxide layer between the sidewalls. A silicon spacer is formed on the sidewalls. An oxidation barrier film is formed on the silicon spacer and on the exposed pad oxide layer. The integrated circuit substrate is then oxidized through the oxidation barrier film to form a device isolating layer. The oxidation barrier film on the exposed pad oxide layer is thinner than the oxidation barrier film on the sidewalls. Thus, oxidation of the silicon spacer is delayed relative to the substrate.
摘要翻译：通过在集成电路基板上形成衬垫氧化物层来隔离集成电路器件。在衬垫层上形成掩模图案。掩模图案包括侧壁，其选择性地暴露在侧壁之间的焊盘氧化物层。在侧壁上形成硅衬垫。在硅间隔物和暴露的焊盘氧化物层上形成氧化阻挡膜。然后将集成电路基板氧化通过氧化阻挡膜以形成器件隔离层。暴露的焊盘氧化物层上的氧化阻挡膜比侧壁上的氧化阻挡膜薄。因此，硅衬垫的氧化相对于衬底延迟。

6. 发明授权

US06893982B2 Method for forming a thin film, methods for forming a gate electrode and transistor using the same, and a gate electrode manufactured using the same 有权
标题翻译：用于形成薄膜的方法，用于形成栅电极的方法和使用其的晶体管，以及使用该方法制造的栅电极
公开(公告)号：US06893982B2
公开(公告)日：2005-05-17
申请号：US10337298
申请日：2003-01-07
申请人： Sung-Eui Kim
发明人： Sung-Eui Kim
IPC分类号： H01L21/336 , H01L21/28 , H01L21/316 , H01L21/31
CPC分类号： H01L21/0217 , H01L21/0223 , H01L21/28247 , H01L21/31662
摘要： A method for forming a thin film on a gate electrode reduces oxidation of the gate electrode during a re-oxidation process to fix the damage to the gate oxide film caused during the formation of the gate electrode pattern. The gate electrode pattern formed in this manner will have reduced defects after re-oxidation. After a gate oxide film is formed on a substrate, a gate electrode pattern is formed on the gate oxide film through an etching process. A thin film that includes nitride is then continuously formed on the gate oxide film and on the gate electrode by utilizing a deposition rate difference between the thin film on the gate oxide film and on the thin film forming the gate electrode. Because of the thin film formed on the gate electrode, oxidation of the gate electrode is reduced during the re-oxidation of the gate oxide film.
摘要翻译：在栅电极上形成薄膜的方法减少了在再氧化过程期间栅电极的氧化，以固定在形成栅极电极图形期间引起的栅极氧化膜的损伤。以这种方式形成的栅电极图案将在再氧化后具有减小的缺陷。在基板上形成栅极氧化膜之后，通过蚀刻工艺在栅极氧化膜上形成栅电极图案。然后通过利用栅极氧化膜上的薄膜和形成栅电极的薄膜之间的沉积速率差，在栅极氧化膜和栅电极上连续地形成包括氮化物的薄膜。由于在栅电极上形成薄膜，在栅极氧化膜的再氧化期间，栅电极的氧化降低。

7. 发明申请

US20140361403A1 SEMICONDUCTOR DEVICES INCLUDING CAPACITORS 有权
标题翻译：包括电容器的半导体器件
公开(公告)号：US20140361403A1
公开(公告)日：2014-12-11
申请号：US14296850
申请日：2014-06-05
申请人： Young-Seung Cho , Sung-Eui Kim , Ji-Young Kim , Hoon Jeong , Chan-Won Kim , Jong-Bom Seo , Seung-Jun Lee , Jun-Soo Lee
发明人： Young-Seung Cho , Sung-Eui Kim , Ji-Young Kim , Hoon Jeong , Chan-Won Kim , Jong-Bom Seo , Seung-Jun Lee , Jun-Soo Lee
IPC分类号： H01L49/02
CPC分类号： H01L28/88 , H01L21/764 , H01L27/10808 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/90
摘要： A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
摘要翻译：半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

8. 发明授权

US07387943B2 Method for forming layer for trench isolation structure 失效
标题翻译：沟槽隔离结构层形成方法
公开(公告)号：US07387943B2
公开(公告)日：2008-06-17
申请号：US10083756
申请日：2002-02-25
申请人： Do-Hyung Kim , Sung-Eui Kim
发明人： Do-Hyung Kim , Sung-Eui Kim
IPC分类号： H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76224
摘要： A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.
摘要翻译：一种在半导体制造工艺中暴露的半导体衬底的表面上形成热氧化层的方法。热氧化层应该是薄的，以最小化由体积膨胀引起的硅衬底缺陷。然后在薄的热氧化物层上形成化学气相沉积（CVD）层，产生所需的厚度。在相同的CVD装置中形成薄的热氧化物层和CVD材料层。结果，可以简化工艺，并且可以防止颗粒导致的污染。

9. 发明授权

US06723662B2 Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with reduced chloride 有权
标题翻译：在使用减少氯化物的湿法或干法氧化法的集成电路器件中形成栅极氧化膜的方法
公开(公告)号：US06723662B2
公开(公告)日：2004-04-20
申请号：US10630101
申请日：2003-07-30
申请人： Kong-soo Lee , Jae-jong Han , Sung-eui Kim
发明人： Kong-soo Lee , Jae-jong Han , Sung-eui Kim
IPC分类号： H01L218242
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02274 , H01L21/02304 , H01L21/02337 , H01L21/28211 , H01L21/31662 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/10894 , H01L27/11
摘要： Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with a reduced amount of chloride are disclosed. A gate oxide film is formed on a substrate on an active region adjacent to a trench isolation region in a first gas atmosphere with a first amount of chloride. The gate oxide film is annealed in a second gas atmosphere including a second amount of chloride that is greater than the first amount.
摘要翻译：公开了使用具有减少量的氯化物的湿式或干式氧化方法在集成电路器件中形成栅极氧化膜的方法。在具有第一量氯化物的第一气体气氛中的与沟槽隔离区相邻的有源区上的衬底上形成栅极氧化膜。栅极氧化膜在包括大于第一量的第二量氯化物的第二气体气氛中退火。

10. 发明授权

US5677232A Methods of fabricating combined field oxide/trench isolation regions 失效
标题翻译：组合场氧化物/沟槽隔离区域的方法
公开(公告)号：US5677232A
公开(公告)日：1997-10-14
申请号：US754889
申请日：1996-11-22
申请人： Sung-eui Kim , Soo-jin Hong
发明人： Sung-eui Kim , Soo-jin Hong
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/76229 , H01L21/76235
摘要： An isolation region is formed on a substrate by forming spaced apart mesas on the substrate. A first insulation region is then formed on the substrate and second insulation regions are formed on the mesas, the first insulation region being disposed between and spaced apart from a respective one of the mesas, a respective one of the second insulation regions capping a respective one of the mesas. Preferably, the first and second insulation regions are formed by forming sidewall spacers adjacent sidewall portions of the mesas and oxidizing portions of the mesas opposite the substrate and a portion of the substrate disposed between the sidewall spacers. Spaced apart trenches are formed in the substrate on opposite sides of the first insulation region, a respective one of the trenches being disposed between the first insulation region and a respective one of the mesas, preferably by removing the sidewall spacers and underlying portions of the substrate. An insulating layer is formed on the substrate, filling the trenches and covering the first insulation region, and the substrate is planarized to remove portions of the insulating layer and the second insulation regions and thereby expose underlying portions of the mesas and leave a third insulation region spanning the trenches.
摘要翻译：通过在衬底上形成间隔开的台面，在衬底上形成隔离区。然后在基板上形成第一绝缘区域，并且在台面上形成第二绝缘区域，第一绝缘区域设置在相应的一个台面之间并与相应的一个台面间隔开，第一绝缘区域中的相应一个覆盖相应的一个的台面。优选地，第一和第二绝缘区域通过形成邻近台面的侧壁部分的侧壁间隔和与衬底相对的台面的氧化部分和设置在侧壁间隔件之间的衬底的一部分而形成。隔开的沟槽在第一绝缘区域的相对侧上的衬底中形成，相应的沟槽设置在第一绝缘区域和相应的台面之间，优选地通过去除侧壁间隔件和衬底的下面部分。在衬底上形成绝缘层，填充沟槽并覆盖第一绝缘区域，并且将衬底平坦化以去除绝缘层和第二绝缘区域的部分，从而暴露台面的下面部分并留下第三绝缘区域跨越壕沟

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