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1. 发明申请

US20050077510A1 Structure for and method of fabricating a high-mobility field-effect transistor 有权
标题翻译：制造高迁移率场效应晶体管的结构和方法
公开(公告)号：US20050077510A1
公开(公告)日：2005-04-14
申请号：US10685013
申请日：2003-10-14
申请人： Jack Chu , Steven Koester , Qiqing Ouyang
发明人： Jack Chu , Steven Koester , Qiqing Ouyang
IPC分类号： H01L29/06 , H01L21/20 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/812 , H01L31/0328 , H01L21/336
CPC分类号： H01L29/66431 , H01L29/7782 , Y10S438/933 , Y10S438/938
摘要： A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.
摘要翻译：制造高迁移率半导体层结构的结构和方法以及包括高迁移率导电沟道的场效应晶体管（MODFET），同时保持反掺杂以控制有害的短沟道效应。 MODFET设计包括高迁移率导电沟道层，其中该方法允许使用诸如离子注入的标准技术形成反相掺杂，并且还允许高迁移率通道紧邻反掺杂而不降解流动性。

2. 发明申请

US20060234481A1 Structure for and method of fabricating a high-mobility field-effect transistor 有权
标题翻译：制造高迁移率场效应晶体管的结构和方法
公开(公告)号：US20060234481A1
公开(公告)日：2006-10-19
申请号：US11209408
申请日：2005-08-23
申请人： Jack Chu , Steven Koester , Qiqing Ouyang
发明人： Jack Chu , Steven Koester , Qiqing Ouyang
IPC分类号： H01L21/425
CPC分类号： H01L29/66431 , H01L29/7782 , Y10S438/933 , Y10S438/938
摘要： A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.
摘要翻译：制造高迁移率半导体层结构的结构和方法以及包括高迁移率导电沟道的场效应晶体管（MODFET），同时保持反掺杂以控制有害的短沟道效应。 MODFET设计包括高迁移率导电沟道层，其中该方法允许使用诸如离子注入的标准技术形成反相掺杂，并且还允许高迁移率通道紧邻反掺杂而不降解流动性。

3. 发明申请

US20050023554A1 Si/SiGe optoelectronic integrated circuits 有权
标题翻译： Si / SiGe光电集成电路
公开(公告)号：US20050023554A1
公开(公告)日：2005-02-03
申请号：US10883434
申请日：2004-07-01
申请人： Jack Chu , Khalid Ismail , Steven Koester , Bernd-Ulrich Klepser
发明人： Jack Chu , Khalid Ismail , Steven Koester , Bernd-Ulrich Klepser
IPC分类号： H01L31/10 , H01L27/144 , H01L31/0312 , H01L31/0352 , H01L31/072
CPC分类号： B82Y20/00 , H01L27/1443 , H01L31/0312 , H01L31/035254
摘要： An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.
摘要翻译：描述了一种集成的光电子电路和制造工艺，其中结合了光电探测器和芯片上的MODFET。该芯片包含单晶半导体衬底，组成SiGe缓冲层，弛豫SiGe层，量子阱层，未掺杂的SiGe间隔层和掺杂的SiGe供应层。光电检测器可以是金属 - 半导体 - 金属（MSM）或p-i-n器件。检测器可以与n型或p型MODFET集成，或者以CMOS配置集成，并且该MODFET可以并入肖特基或绝缘栅。本发明克服了通过使用表面生长的Si / SiGe异质结构层制造用于850nm工作的Si制造兼容的单片高速光电子电路的问题。

4. 发明申请

US20050184354A1 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
标题翻译：制造高速CMOS兼容的绝缘体上的光电探测器的结构和方法
公开(公告)号：US20050184354A1
公开(公告)日：2005-08-25
申请号：US10785894
申请日：2004-02-24
申请人： Jack Chu , Gabriel Dehlinger , Alfred Grill , Steven Koester , Qiging Ouyang , Jeremy Schaub
发明人： Jack Chu , Gabriel Dehlinger , Alfred Grill , Steven Koester , Qiging Ouyang , Jeremy Schaub
IPC分类号： H01L31/101 , H01L31/075
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层来隔离衬底中产生的载流子，通过利用Ge吸收层在宽谱上具有高量子效率，通过利用薄的吸收层和窄电极间隔的低电压操作以及兼容性来实现高带宽通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

5. 发明申请

US20110037175A1 INTERCONNECTION BETWEEN SUBLITHOGRAPHIC-PITCHED STRUCTURES AND LITHOGRAPHIC-PITCHED STRUCTURES 有权
标题翻译：分层抛光结构与平面抛光结构之间的互连
公开(公告)号：US20110037175A1
公开(公告)日：2011-02-17
申请号：US12540759
申请日：2009-08-13
申请人： Sarunya Bangsaruntip , Daniel C. Edelstein , William D. Hinsberg , Ho-Cheol Kim , Steven Koester , Paul M. Solomon
发明人： Sarunya Bangsaruntip , Daniel C. Edelstein , William D. Hinsberg , Ho-Cheol Kim , Steven Koester , Paul M. Solomon
IPC分类号： H01L23/48 , H05K1/11 , B05D5/12 , G03F7/20
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76838 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.
摘要翻译：形成了亚光刻间距结构和光刻凸出结构之间的互连。具有亚光刻间距的多条导线可以被光刻图案化并且沿着与多根导线的长度方向成小于45度的角度的切割。或者，与均聚物混合的共聚物可以放置在凹陷区域中并自对准以形成在恒定宽度区域具有亚光刻间距的多条导线，以及在梯形区域处的相邻线之间的光刻尺寸。或者，具有亚光刻间距的第一多个导线和具有光刻间距的第二多个导线可以形成在相同的水平或不同的位置。

6. 发明申请

US20080001173A1 BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS 审中-公开
公开(公告)号：US20080001173A1
公开(公告)日：2008-01-03
申请号：US11767188
申请日：2007-06-22
申请人： Edward Kiewra , Steven Koester , Devendra Sadana , Ghavam Shahidi , Yanning Sun
发明人： Edward Kiewra , Steven Koester , Devendra Sadana , Ghavam Shahidi , Yanning Sun
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7787 , H01L29/66462
摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

7. 发明授权

US07989900B2 Semiconductor structure including gate electrode having laterally variable work function 有权
标题翻译：半导体结构包括具有横向可变功函数的栅电极
公开(公告)号：US07989900B2
公开(公告)日：2011-08-02
申请号：US12544452
申请日：2009-08-20
申请人： Wilfried Haensch , Steven Koester , Amlan Majumdat
发明人： Wilfried Haensch , Steven Koester , Amlan Majumdat
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/28026 , H01L21/28105 , H01L21/823842 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/4232 , H01L29/4908 , H01L29/4983 , H01L29/66545 , H01L29/785
摘要： A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally variable work function provides enhanced electrical performance within an undoped channel field effect transistor device.
摘要翻译：诸如CMOS结构的半导体结构包括具有横向可变功函数的栅电极。具有横向可变功函数的栅电极可以使用成角度离子注入法或顺序分层方法形成。具有横向可变功函数的栅电极在未掺杂的沟道场效应晶体管器件内提供增强的电性能。

8. 发明授权

US08263477B2 Structure for use in fabrication of PiN heterojunction TFET 有权
标题翻译：用于制造PiN异质结TFET的结构
公开(公告)号：US08263477B2
公开(公告)日：2012-09-11
申请号：US12684331
申请日：2010-01-08
申请人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译：制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。

9. 发明申请

US20110220805A1 FET RADIATION MONITOR 有权
标题翻译： FET辐射监测器
公开(公告)号：US20110220805A1
公开(公告)日：2011-09-15
申请号：US12719962
申请日：2010-03-09
申请人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
发明人： Michael Gordon , Steven Koester , Kenneth Rodbell , Jeng-Bang Yau
IPC分类号： G01T1/24 , H01L31/08
CPC分类号： H01L31/119
摘要： A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.
摘要翻译：半导体器件包括半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。一种用于辐射监测的方法，所述方法包括将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。

10. 发明申请

US20110169051A1 Structure for Use in Fabrication of PiN Heterojunction TFET 有权
标题翻译：用于制造PiN异质结TFET的结构
公开(公告)号：US20110169051A1
公开(公告)日：2011-07-14
申请号：US12684331
申请日：2010-01-08
申请人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译：制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。

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