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1. 发明申请

WO2009094281A1 ANISOTROPIC STRESS GENERATION BY STRESS-GENERATING LINERS HAVING A SUBLITHOGRAPHIC WIDTH 审中-公开
标题翻译：通过应力产生具有子平面宽度的衬垫的各向异性应力生成
公开(公告)号：WO2009094281A1
公开(公告)日：2009-07-30
申请号：PCT/US2009/031043
申请日：2009-01-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CLEVENGER, Lawrence, A. , DORIS, Bruce, B. , HUANG, Elbert, E. , PURUSHOTHAMAN, Sampath , RADENS, Carl, J.
发明人： CLEVENGER, Lawrence, A. , DORIS, Bruce, B. , HUANG, Elbert, E. , PURUSHOTHAMAN, Sampath , RADENS, Carl, J.
IPC分类号： H01L21/335
CPC分类号： H01L21/31144 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/84 , H01L27/1203 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： A protruding structure having a linear edge is formed on a substrate (8). The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate (8). A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner (50), and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge (41) of the protruding structure. Linear nanoscale stripes (50) are formed in the polymeric resist which is self-aligning and self- assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sub lithographic width. The linear stress-generating stripes (50) provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.
摘要翻译：在基板（8）上形成具有直线边缘的突出结构。突出结构可以是场效应晶体管的栅极线。应力产生衬垫沉积在衬底（8）上。含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬垫（50）上，并进行退火以允许不混溶组分相分离。聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘（41）而形成嵌套线图案。在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹（50）。将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。线性应力产生条纹（50）沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

2. 发明申请

WO2009021091A1 CORRUGATED INTERFACES FOR MULTILAYERED INTERCONNECTS 审中-公开
标题翻译：多层互连的接口接口
公开(公告)号：WO2009021091A1
公开(公告)日：2009-02-12
申请号：PCT/US2008/072420
申请日：2008-08-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HUANG, Elbert, E. , PURUSHOTHAMAN, Sampath , RADENS, Carl, J.
发明人： CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HUANG, Elbert, E. , PURUSHOTHAMAN, Sampath , RADENS, Carl, J.
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H05K3/40 , H01B17/66 , H01L21/0337 , H01L21/31144 , H01L21/76822 , H01L23/53295 , H01L2924/0002 , Y10T156/1039 , Y10T156/1082 , Y10T428/24521 , Y10T428/24529 , Y10T428/24537 , Y10T428/24612 , Y10T428/24711 , H01L2924/00
摘要： Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers (114) to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.
摘要翻译：包含在互连叠层中具有纳米级波纹界面的界面的介电复合结构提供了增强的粘合强度和界面断裂韧性。还描述了还包括波纹粘合促进剂层（114）以进一步增加固有界面粘合性的复合结构。还描述了使用自组装聚合物体系和图案转移方法形成纳米级波纹界面以实现这些结构的方法。

3. 发明申请

WO2007027813A2 MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：微孔MEMS器件及其制造方法
公开(公告)号：WO2007027813A2
公开(公告)日：2007-03-08
申请号：PCT/US2006/033924
申请日：2006-08-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HSU, Louis, C. , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , RADENS, Carl, J. , WONG, Keith Kwong, Hon , YANG, Chih-chao
发明人： HSU, Louis, C. , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , RADENS, Carl, J. , WONG, Keith Kwong, Hon , YANG, Chih-chao
IPC分类号： H01P1/10
CPC分类号： H01H50/005 , H01H2050/007 , Y10T29/4902 , Y10T29/49105 , Y10T29/49147
摘要： A MEM switch is described having a free moving element (140) within in micro- cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180, 200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) preferably also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_l, M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When the chip is not mounted with the correct orientation, gravity cannot be used. In such an instance, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.
摘要翻译：描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200）微腔（40）; 以及优选也由磁性材料制成的自由移动的开关元件（140）。通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_1，M_r）短路，从而闭合开关。当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。当芯片未正确安装时，重力不能使用。在这种情况下，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

4. 发明申请

WO2006088534A1 INTERCONNECT STRUCTURES WITH ENCASING CAP AND METHODS OF MAKING THEREOF 审中-公开
标题翻译：具有加密帽的互连结构及其制造方法
公开(公告)号：WO2006088534A1
公开(公告)日：2006-08-24
申请号：PCT/US2005/043465
申请日：2005-12-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HSU, Louis, C. , RADENS, Carl, J. , STANDAERT, Theodorus, E. , WONG, Keith, Kwong, Hon , YANG, Chih-Chao
发明人： CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HSU, Louis, C. , RADENS, Carl, J. , STANDAERT, Theodorus, E. , WONG, Keith, Kwong, Hon , YANG, Chih-Chao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，包括：在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

5. 发明申请

WO2009061698A1 STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETS 审中-公开
标题翻译：紧凑型长通道FET的结构和方法
公开(公告)号：WO2009061698A1
公开(公告)日：2009-05-14
申请号：PCT/US2008/082226
申请日：2008-11-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , RADENS, Carl, J. , STAMPER, Anthony, K.
发明人： DORIS, Bruce, B. , RADENS, Carl, J. , STAMPER, Anthony, K.
IPC分类号： H01L29/00
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate (12) in which the at least one FET includes a long channel length and/or a wide channel width (11) and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，包括位于半导体衬底（12）的表面之上和之内的至少一个FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度（11），以及制造同样提供。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

6. 发明申请

WO2003107430A1 ENHANCED STRUCTURE AND METHOD FOR BURIED LOCAL INTERCONNECTS 审中-公开
标题翻译：增强的局部互连的结构和方法
公开(公告)号：WO2003107430A1
公开(公告)日：2003-12-24
申请号：PCT/US2002/019238
申请日：2002-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DIVAKARUNI, Ramachandra , GLUSCHENKOV, Oleg , MANDELMAN, Jack, A. , RADENS, Carl, J. , WONG, Robert, C.
发明人： DIVAKARUNI, Ramachandra , GLUSCHENKOV, Oleg , MANDELMAN, Jack, A. , RADENS, Carl, J. , WONG, Robert, C.
IPC分类号： H01L29/40
CPC分类号： H01L21/743 , H01L21/76895 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/42384 , H01L29/7839 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.
摘要翻译：公开了一种用于在衬底的单晶半导体层（12）中形成集成电路的掩埋互连（10）的结构和方法。掩埋互连由沉积导体形成，并且具有一个或多个与形成在单晶半导体层中的电子器件（20）的单晶区接触的垂直侧壁（18）。

7. 发明申请

WO2006055357A3 TRENCH CAPACITOR WITH HYBRID SURFACE ORIENTATION SUBSTRATE 审中-公开
公开(公告)号：WO2006055357A3
公开(公告)日：2006-05-26
申请号：PCT/US2005/040524
申请日：2005-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHENG, Kangguo , RADENS, Carl, J.
发明人： CHENG, Kangguo , RADENS, Carl, J.
IPC分类号： H01L21/8242
摘要： Methods of forming a deep trench capacitor memory device (50) and logic devices (32, 40) on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.

8. 发明申请

WO2007082227A2 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：WO2007082227A2
公开(公告)日：2007-07-19
申请号：PCT/US2007/060317
申请日：2007-01-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHENG, Kangguo , DIVAKARUNI, Ramachandra , MANDELMAN, Jack, A. , RADENS, Carl, J. , WANG, Geng
发明人： CHENG, Kangguo , DIVAKARUNI, Ramachandra , MANDELMAN, Jack, A. , RADENS, Carl, J. , WANG, Geng
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括作为整体电容源连接在一起的多个电容器（102）。第一存取晶体管（104）耦合在所述多个电容器中的第一电容器和第一位线之间并且第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

9. 发明申请

WO2002086904A3 VERTICAL TRANSISTOR TRENCH CAPACITOR MEMORY CELL AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：WO2002086904A3
公开(公告)日：2002-10-31
申请号：PCT/US2002/010892
申请日：2002-04-08
申请人： INFINEON TECHNOLOGIES AG , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： DYER, Thomas, W. , KUDELKA, Stephan, P. , JAIPRAKASH, Venkatachaiam, C. , RADENS, Carl, J.
IPC分类号： H01L21/8242
摘要： A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

10. 发明申请

WO2002037542A3 METHOD FOR TRENCH CAPACITOR DRAM CELL WITHOUT FLOATING-WELL EFFECTS 审中-公开
公开(公告)号：WO2002037542A3
公开(公告)日：2002-05-10
申请号：PCT/US2001/046921
申请日：2001-11-05
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： MANDELMAN, Jack, A. , DIVAKARUNI, Ramachandra , RADENS, Carl, J. , KUDELKA, Stephan
IPC分类号： H01L21/8242
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of V¿blh? of about 1.5 V and substantially free of floating-well effects. In accordance with the present invention, each shallow isolation trench region (105) has a depth that is substantially above the one-sided buried-strap outdiffusion region (70) thereby not cutting into the one-sided buried-strap outdiffusion region, yet being deep enough to isolation adjacent bitline diffusion regions that abut each vertical memory cell. Electrical continuity between the deep portion of the P-well (biased at V bb’ typically-0.5V) and the portion of the P-well above the strap is obtained by hole flow around the depletion region surrounding the strap diffusion. In accordance with the present invention, the SIT regions are sufficiently shallow (greater that 40nm above the strap diffusion junction) to allow a non-depletion portion of the P-well to remain between the strap diffusion and the bottom of the SIP. Since the conductive region which provides P-well continuity is original single crystal silicon, junction leakage due to a depletion region abutting a polycrystalline contact is not a concern.

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