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    • 1. 发明申请
    • STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETS
    • 紧凑型长通道FET的结构和方法
    • WO2009061698A1
    • 2009-05-14
    • PCT/US2008/082226
    • 2008-11-03
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONDORIS, Bruce, B.RADENS, Carl, J.STAMPER, Anthony, K.
    • DORIS, Bruce, B.RADENS, Carl, J.STAMPER, Anthony, K.
    • H01L29/00
    • H01L29/1037H01L29/6659H01L29/66621
    • A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate (12) in which the at least one FET includes a long channel length and/or a wide channel width (11) and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
    • 一种紧凑的半导体结构,包括位于半导体衬底(12)的表面之上和之内的至少一个FET,其中所述至少一个FET包括长沟道长度和/或宽沟道宽度(11),以及制造 同样提供。 在一些实施例中,有序的纳米尺寸图案在垂直于电流的方向上取向。 在这样的实施例中,FET具有长的沟道长度。 在其他实施例中,有序的纳米尺寸图案在平行于电流流动的方向上取向。 在这样的实施例中,FET具有宽的通道宽度。 在另一个实施例中,一个有序的纳米尺寸图案在垂直于电流的方向上定向,而另一个有序的纳米尺寸图案在平行于电流的方向上取向。 在这样的实施例中,提供具有长沟道长度和宽沟道宽度的FET。
    • 5. 发明申请
    • PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    • 在混合方向晶体管中对充电损害的保护
    • WO2007115146A2
    • 2007-10-11
    • PCT/US2007/065604
    • 2007-03-30
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONHOOK, Terence, B.MOCUTA, Anda, C.SLEIGHT, Jeffrey, W.STAMPER, Anthony, K.
    • HOOK, Terence, B.MOCUTA, Anda, C.SLEIGHT, Jeffrey, W.STAMPER, Anthony, K.
    • A61K31/203A61K9/127
    • H01L21/84H01L21/823807H01L21/823878H01L27/0251H01L27/0629H01L27/1203H01L27/1207
    • A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
    • 芯片包括CMOS结构,其具有设置在半导体衬底(50)的第一区域(24)中的本体器件(20),该半导体衬底(50)与衬底的下伏体区域(18)导通连通,第一区域(24)和 本体区域(20)具有第一晶体取向。 SOI器件(10)设置在通过掩埋介电层(16)与衬底的本体区域分离的绝缘体上半导体(“SOI”)层14中,SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中,体器件包括p型场效应晶体管(“PFET”),并且SOI器件包括n型场效应晶体管(“NFET”)器件。 或者,体器件可以包括NFET,并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体(21)导电连通的栅极导体(11)时,SOI器件可能会发生充电损坏,除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时,二极管可操作以将放电电流传导到体区。