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1. 发明申请

WO2007082227A3 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：WO2007082227A3
公开(公告)日：2008-09-25
申请号：PCT/US2007060317
申请日：2007-01-10
申请人： IBM , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
发明人： CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , RADENS CARL J , WANG GENG
IPC分类号： G11C11/24 , H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

2. 发明申请

WO2012106056A2 SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW 审中-公开
标题翻译：用于高K /金属栅工艺流程的自对准接触
公开(公告)号：WO2012106056A2
公开(公告)日：2012-08-09
申请号：PCT/US2012/020020
申请日：2012-01-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , RAMACHANDRAN, Ravikumar , DIVAKARUNI, Ramachandra , LI, Ying
发明人： RAMACHANDRAN, Ravikumar , DIVAKARUNI, Ramachandra , LI, Ying
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/401 , H01L21/76895 , H01L21/76897 , H01L29/49 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure is provided that includes a semiconductor substrate 12 having a plurality of gate stacks 14' located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer 42, a work function metal layer 44 and a conductive metal 46. A spacer 22 is located on sidewalls of each gate stack and a self- aligned dielectric liner 30 is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner 30 is present on an upper surface of a semiconductor metal alloy 28. A contact metal 34 is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner 30. The structure also includes another contact metal 60 having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.
摘要翻译：提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅叠层14'的半导体衬底12。每个栅极堆叠包括从底部到顶部的高k栅极电介质层42，功函数金属层44和导电金属46.间隔物22位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫30是存在于每个间隔件的上表面上。每个自对准电介质衬垫30的底表面存在于半导体金属合金28的上表面上。接触金属34位于相邻的栅极叠层之间，并通过自对准绝缘衬垫30与每个栅极堆叠分开。该结构还包括另一个接触金属60，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及另一部分，其位于与其中一个栅极叠层的导电金属直接接触的位置。还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

3. 发明申请

WO2007082227A2 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 审中-公开
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：WO2007082227A2
公开(公告)日：2007-07-19
申请号：PCT/US2007/060317
申请日：2007-01-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHENG, Kangguo , DIVAKARUNI, Ramachandra , MANDELMAN, Jack, A. , RADENS, Carl, J. , WANG, Geng
发明人： CHENG, Kangguo , DIVAKARUNI, Ramachandra , MANDELMAN, Jack, A. , RADENS, Carl, J. , WANG, Geng
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括作为整体电容源连接在一起的多个电容器（102）。第一存取晶体管（104）耦合在所述多个电容器中的第一电容器和第一位线之间并且第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

4. 发明申请

WO2007023011A2 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
标题翻译：双端口增益电池与侧面和顶部门控读取晶体管
公开(公告)号：WO2007023011A2
公开(公告)日：2007-03-01
申请号：PCT/EP2006063581
申请日：2006-06-27
申请人： IBM , IBM UK , MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
发明人： MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/12
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。本领域已知各种增益单元布局。本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

5. 发明申请

WO2007137946A3 TRENCH WIDENING WITHOUT MERGING 审中-公开
标题翻译：没有合并的TRENCH扩大
公开(公告)号：WO2007137946A3
公开(公告)日：2008-03-13
申请号：PCT/EP2007054769
申请日：2007-05-16
申请人： IBM , IBM UK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA
发明人： CHENG KANGGUO , DIVAKARUNI RAMACHANDRA
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法包括提供半导体结构的步骤。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围周围。

6. 发明申请

WO2007137946A2 TRENCH WIDENING WITHOUT MERGING 审中-公开
标题翻译：没有合并的TRENCH扩大
公开(公告)号：WO2007137946A2
公开(公告)日：2007-12-06
申请号：PCT/EP2007/054769
申请日：2007-05-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHENG, Kangguo , DIVAKARUNI, Ramachandra
发明人： CHENG, Kangguo , DIVAKARUNI, Ramachandra
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法包括提供半导体结构的步骤。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围周围。

7. 发明申请

WO2007115002A2 SELF-ALIGNED BODY CONTACT FOR AN SEMICONDUCTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：绝缘子半导体器件的自对准身体接触器及其制造方法
公开(公告)号：WO2007115002A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/064380
申请日：2007-03-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DIVAKARUNI, Ramachandra , CHENG, Kangguo
发明人： DIVAKARUNI, Ramachandra , CHENG, Kangguo
IPC分类号： B01D53/04 , C01B31/20
CPC分类号： H01L29/7827 , H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a body contact (215) for an semiconductor-on-insulator trench device. The method including: forming set of mandrels (190) on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers (195) on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening (197) in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench (200) in the substrate in the opening; and filling the contact trench with an electrically conductive material (210) to form the contact.
摘要翻译：一种形成用于绝缘体上半导体沟槽器件的体接触（215）的结构和方法。该方法包括：在基板的顶表面上形成一组心轴（190），该心轴组的每个心轴布置在多边形的不同角上并在衬底的顶表面上方延伸，一组心轴等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件（195），每个相邻的一对心轴的侧壁间隔件彼此合并并形成在多边形的内部区域中限定开口（197）的不间断的壁，区域的基板暴露在开口中; 蚀刻开口中的衬底中的接触沟槽（200）; 以及用导电材料（210）填充所述接触沟槽以形成所述接触。

8. 发明申请

WO2009053251A1 INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 审中-公开
标题翻译：多金属门工作功能结构的整合方案
公开(公告)号：WO2009053251A1
公开(公告)日：2009-04-30
申请号：PCT/EP2008/063533
申请日：2008-10-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHENG, Kangguo , CHUDZIK, Michael , DIVAKARUNI, Ramachandra , WANG, Geng , WONG, Robert , YANG, Haining
发明人： CHENG, Kangguo , CHUDZIK, Michael , DIVAKARUNI, Ramachandra , WANG, Geng , WONG, Robert , YANG, Haining
IPC分类号： H01L21/8238 , H01L21/8239 , H01L29/51 , H01L29/49 , H01L27/105
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

9. 发明申请

WO2007023011B1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：WO2007023011B1
公开(公告)日：2007-07-12
申请号：PCT/EP2006063581
申请日：2006-06-27
申请人： IBM , IBM UK , MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
发明人： MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

10. 发明申请

WO2007023011A3 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
公开(公告)号：WO2007023011A3
公开(公告)日：2007-03-01
申请号：PCT/EP2006/063581
申请日：2006-06-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MANDELMAN, Jack , CHENG, Kangguo , DIVAKARUNI, Ramachandra , RADENS, Carl , WANG, Geng
发明人： MANDELMAN, Jack , CHENG, Kangguo , DIVAKARUNI, Ramachandra , RADENS, Carl , WANG, Geng
IPC分类号： H01L27/108 , H01L21/8242
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

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