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    • 6. 发明申请
    • DUAL STRESSED SOI SUBSTRATES
    • 双应力SOI衬底
    • WO2006065759A3
    • 2007-06-14
    • PCT/US2005044957
    • 2005-12-13
    • IBMCHIDAMBARRAO DURESETIDOKUMACI OMER HDORIS BRUCE BGLUSCHENKOV OLEGZHU HUILONG
    • CHIDAMBARRAO DURESETIDOKUMACI OMER HDORIS BRUCE BGLUSCHENKOV OLEGZHU HUILONG
    • H01L21/84H01L27/01
    • H01L21/84H01L27/1203H01L29/7843Y10S438/938
    • The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .
    • 本发明提供一种应变Si结构,其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上,应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层,其中所述压缩介电层将拉伸应力传递到所述第一半导体层,以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层,其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物,例如Si 3 N 4 N 4。