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1. 发明申请

WO2006107669A3 METHOD OF PRODUCING HIGHLY STRAINED PECVD SILICON NITRIDE THIN FILMS AT LOW TEMPERATURE 审中-公开
标题翻译：在低温下生产高应变PECVD硅氮化物薄膜的方法
公开(公告)号：WO2006107669A3
公开(公告)日：2009-04-09
申请号：PCT/US2006011391
申请日：2006-03-29
申请人： IBM , BELYANSKY MICHAEL P , GLUSCHENKOV OLEG , LI YING , MALLIKARJUNAN ANUPAMA
发明人： BELYANSKY MICHAEL P , GLUSCHENKOV OLEG , LI YING , MALLIKARJUNAN ANUPAMA
IPC分类号： H01L21/26
CPC分类号： H01L21/3185 , C23C16/345 , C23C16/45523 , H01L21/823807 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material (14) on at least a surface of a substrate (12), said first portion (18) having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified (20) such that the first state of mechanical strain is not substantiaUydtered,\vhile increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times (20, 2OA, 20B) to obtain a preselected and desired thickness for the stressor.
摘要翻译：提供了一种通过改变这种压力源的内部结构来提高非晶薄膜应力的应力水平的方法。该方法包括首先在衬底（12）的至少一个表面上形成非晶膜应力材料（14）的第一部分，所述第一部分（18）具有限定第一应力值的第一机械应变状态。在成形步骤之后，无定形薄膜应力材料的第一部分被致密化（20），使得机械应变的第一状态没有被证实，即增加第一应力值。在一些实施例中，形成和致密化的步骤重复任意次数（20,20A，20B），以获得应力源的预选和期望的厚度。

2. 发明申请

WO2007038237A2 MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
标题翻译：在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流
公开(公告)号：WO2007038237A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/036916
申请日：2006-09-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , DOKUMACI, Omer , GLUSCHENKOV, Oleg , BELYANSKY, Michael
发明人： CHIDAMBARRAO, Dureseti , DOKUMACI, Omer , GLUSCHENKOV, Oleg , BELYANSKY, Michael
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/512 , H01L21/26586 , H01L21/31155 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.
摘要翻译：本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。

3. 发明申请

WO2003107430A1 ENHANCED STRUCTURE AND METHOD FOR BURIED LOCAL INTERCONNECTS 审中-公开
标题翻译：增强的局部互连的结构和方法
公开(公告)号：WO2003107430A1
公开(公告)日：2003-12-24
申请号：PCT/US2002/019238
申请日：2002-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DIVAKARUNI, Ramachandra , GLUSCHENKOV, Oleg , MANDELMAN, Jack, A. , RADENS, Carl, J. , WONG, Robert, C.
发明人： DIVAKARUNI, Ramachandra , GLUSCHENKOV, Oleg , MANDELMAN, Jack, A. , RADENS, Carl, J. , WONG, Robert, C.
IPC分类号： H01L29/40
CPC分类号： H01L21/743 , H01L21/76895 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/42384 , H01L29/7839 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.
摘要翻译：公开了一种用于在衬底的单晶半导体层（12）中形成集成电路的掩埋互连（10）的结构和方法。掩埋互连由沉积导体形成，并且具有一个或多个与形成在单晶半导体层中的电子器件（20）的单晶区接触的垂直侧壁（18）。

4. 发明申请

WO2008134686A3 SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD 审中-公开
标题翻译：硅锗绝缘双极晶体管结构与方法
公开(公告)号：WO2008134686A3
公开(公告)日：2009-12-30
申请号：PCT/US2008061938
申请日：2008-04-30
申请人： IBM , KRISHNASAMY RAJENDRAN , GLUSCHENKOV OLEG , SCHONENBERG KATHRYN T
发明人： KRISHNASAMY RAJENDRAN , GLUSCHENKOV OLEG , SCHONENBERG KATHRYN T
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/2253 , H01L21/26513 , H01L21/324 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/7378
摘要： Disclosed is an improved semiconductor structure 150 (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor 100) having a narrow essentially interstitial-free SIC pedestal 120 with minimal overlap of the extrinsic base 104. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base 103 and collector space-charge regions than can be achieved with conventional technology.
摘要翻译：公开了一种改进的半导体结构150（例如，硅锗（SiGe）异质结双极晶体管100），其具有窄的基本上无间隙的SIC基座120，其外部基极104具有最小的重叠。此外，公开了一种形成使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本上无间隙的收集器的晶体管。因此，所得到的SiGe HBT晶体管可以制造成具有比用常规技术可以实现的更窄的基极103和集电极空间电荷区域。

5. 发明申请

WO2007112432A3 EPITAXY OF SILICON-CARBON SUBSTITUTIONAL SOLID SOLUTIONS BY ULTRA-FAST ANNEALING OF AMORPHOUS MATERIAL 审中-公开
标题翻译：通过超弹性非晶态材料退火的硅碳取代固体溶液外延
公开(公告)号：WO2007112432A3
公开(公告)日：2009-03-26
申请号：PCT/US2007065324
申请日：2007-03-28
申请人： IBM , LIU YAOCHENG , GLUSCHENKOV OLEG , RIM KERN , MADAN ANITA , HOLT JUDSON
发明人： LIU YAOCHENG , GLUSCHENKOV OLEG , RIM KERN , MADAN ANITA , HOLT JUDSON
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/2022 , H01L21/2026 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y
摘要翻译：可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。退火优选是闪光退火或激光退火。该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

6. 发明申请

WO2006065759A3 DUAL STRESSED SOI SUBSTRATES 审中-公开
标题翻译：双应力SOI衬底
公开(公告)号：WO2006065759A3
公开(公告)日：2007-06-14
申请号：PCT/US2005044957
申请日：2005-12-13
申请人： IBM , CHIDAMBARRAO DURESETI , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , ZHU HUILONG
发明人： CHIDAMBARRAO DURESETI , DOKUMACI OMER H , DORIS BRUCE B , GLUSCHENKOV OLEG , ZHU HUILONG
IPC分类号： H01L21/84 , H01L27/01
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

7. 发明申请

WO2005050701A3 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 审中-公开
公开(公告)号：WO2005050701A3
公开(公告)日：2005-06-02
申请号：PCT/US2004/037434
申请日：2004-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , BELYANSKY, Michael, P. , BOYD, Diane, C. , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg
发明人： DORIS, Bruce, B. , BELYANSKY, Michael, P. , BOYD, Diane, C. , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg
IPC分类号： H01L31/119
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

8. 发明申请

WO2008134686A2 SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD 审中-公开
标题翻译：硅锗绝缘双极晶体管结构与方法
公开(公告)号：WO2008134686A2
公开(公告)日：2008-11-06
申请号：PCT/US2008/061938
申请日：2008-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KRISHNASAMY, Rajendran , GLUSCHENKOV, Oleg , SCHONENBERG, Kathryn, T.
发明人： KRISHNASAMY, Rajendran , GLUSCHENKOV, Oleg , SCHONENBERG, Kathryn, T.
IPC分类号： H01L21/331 , H01L31/11 , H01L31/117 , H01L31/00
CPC分类号： H01L29/66242 , H01L21/2253 , H01L21/26513 , H01L21/324 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/7378
摘要： Disclosed is an improved semiconductor structure 150 (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor 100) having a narrow essentially interstitial-free SIC pedestal 120 with minimal overlap of the extrinsic base 104. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base 103 and collector space-charge regions than can be achieved with conventional technology.
摘要翻译：公开了一种改进的半导体结构150（例如，硅锗（SiGe）异质结双极晶体管100），其具有窄的基本上无间隙的SIC基座120，其外部基极104具有最小的重叠。此外，公开了一种形成使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本上无间隙的收集器的晶体管。因此，所得到的SiGe HBT晶体管可以制造成具有比用常规技术可以实现的更窄的基极103和集电极空间电荷区域。

9. 发明申请

WO2008085686A2 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE 审中-公开
标题翻译：具有硅酸盐的移动增强MOSFET的结构和方法
公开(公告)号：WO2008085686A2
公开(公告)日：2008-07-17
申请号：PCT/US2007088266
申请日：2007-12-20
申请人： IBM , LIU YAOCHANG , CHIDAMBARRAO DURESETI , RIM KERN , GLUSCHENKOV OLEG , MO RENEE T , HOLT JUDSON R
发明人： LIU YAOCHANG , CHIDAMBARRAO DURESETI , RIM KERN , GLUSCHENKOV OLEG , MO RENEE T , HOLT JUDSON R
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

10. 发明申请

WO2006115914A1 ULTRA-THIN HF-DOPED SILICON OXYNITRIDE FILM FOR HIGH PERFORMANCE CMOS APPLICATIONS AND METHOD OF MANUFACTURE 审中-公开
标题翻译：用于高性能CMOS应用的超薄薄膜硅氧烷膜及其制造方法
公开(公告)号：WO2006115914A1
公开(公告)日：2006-11-02
申请号：PCT/US2006/014622
申请日：2006-04-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ZHU, Wenjuan , CHUDZIK, Michael P , GLUSCHENKOV, Oleg , PARK, Dae-Gyu , SEKIGUCHI, Akihisa
发明人： ZHU, Wenjuan , CHUDZIK, Michael P , GLUSCHENKOV, Oleg , PARK, Dae-Gyu , SEKIGUCHI, Akihisa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/28097 , H01L21/28229 , H01L21/823857 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controUing stable material on top of a base gate dielectric layer (53), and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer (53).
摘要翻译：一种半导体结构及其制造方法，包括在基极栅介质层（53）的顶部形成均匀的扩散控制稳定材料缓冲层，然后形成含有过渡金属原子源的均匀层，以及然后对结构进行退火，以使过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅介质层（53）。

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