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1. 发明授权

US07746688B2 PRAM and method of firing memory cells 有权
标题翻译： PRAM和烧存存储单元的方法
公开(公告)号：US07746688B2
公开(公告)日：2010-06-29
申请号：US11933536
申请日：2007-11-01
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim , Woo-yeong Cho , Chang-han Choi , Ki-won Lim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim , Woo-yeong Cho , Chang-han Choi , Ki-won Lim
IPC分类号： G11C11/00
CPC分类号： G11C8/06 , G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/12005 , G11C29/50 , G11C2013/0083 , G11C2013/0092
摘要： A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.
摘要翻译： PRAM包括相变存储单元的存储单元阵列和接收外部提供的第一电压的写入电路，并且在正常操作模式中提供用于将数据写入存储单元的写入脉冲。写入电路还接收高于第一电压的外部提供的第二电压，并且向至少一个点火故障相变存储单元提供点火脉冲。

2. 发明授权

US07283387B2 Phase change random access memory device having variable drive voltage circuit 有权
标题翻译：具有可变驱动电压电路的相变随机存取存储器件
公开(公告)号：US07283387B2
公开(公告)日：2007-10-16
申请号：US11316256
申请日：2005-12-23
申请人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.
摘要翻译：相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的数据线和将数据线连接到读出放大器单元的控制节点。在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

3. 发明申请

US20070058425A1 Phase change random access memory device having variable drive voltage circuit 有权
公开(公告)号：US20070058425A1
公开(公告)日：2007-03-15
申请号：US11316256
申请日：2005-12-23
申请人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

4. 发明授权

US07580295B2 Semiconductor memory device and memory system including semiconductor memory device 有权
标题翻译：半导体存储器件和包括半导体存储器件的存储器系统
公开(公告)号：US07580295B2
公开(公告)日：2009-08-25
申请号：US11850128
申请日：2007-09-05
申请人： Kwang-jin Lee , Woo-yeong Cho , Hye-jin Kim
发明人： Kwang-jin Lee , Woo-yeong Cho , Hye-jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/22
摘要： A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.
摘要翻译：半导体存储器件包括包括第一类型存储单元的存储单元阵列。存储单元阵列响应于设计用于包括除了第一类型之外的类型的存储器单元的存储单元阵列的操作的信号执行写入和读取操作。

5. 发明授权

US07859882B2 Resistive memory device and method of writing data 有权
标题翻译：电阻式存储器件及数据写入方法
公开(公告)号：US07859882B2
公开(公告)日：2010-12-28
申请号：US11844511
申请日：2007-08-24
申请人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang
发明人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C13/00 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2213/79
摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.
摘要翻译：提供了一种电阻式存储器件。电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子线路和连接到相应字线的控制终端。本地源极线通常连接到两个相邻行的单元晶体管的第二端子。

6. 发明申请

US20070086235A1 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070086235A1
公开(公告)日：2007-04-19
申请号：US11529323
申请日：2006-09-29
申请人： Du-eung Kim , Chang--soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang--soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

7. 发明授权

US07450415B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07450415B2
公开(公告)日：2008-11-11
申请号：US11640956
申请日：2006-12-19
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
摘要翻译：提供了相变存储器件。相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

8. 发明申请

US20070159878A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20070159878A1
公开(公告)日：2007-07-12
申请号：US11648558
申请日：2007-01-03
申请人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
发明人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
IPC分类号： G11C5/06 , G11C11/00 , G11C8/00
CPC分类号： G11C7/18 , G11C8/12 , G11C13/0004 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
摘要翻译：相变存储器件包括：半导体衬底，其包括多个相变存储器单元;多个局部位线，其延伸在所述半导体衬底上;所述多个局部位线中的每一个耦合到所述多个相变存储器单元; 以及在所述多个局部位线上延伸的多个全局位线，所述多个全局位线中的每一条选择性地耦合到所述多个局部位线。多个全局位线位于半导体衬底上的两个或更多个不同的布线层上。

9. 发明申请

US20060256612A1 Phase change memory device and method of driving word line thereof 有权
标题翻译：相变存储器件及其驱动字线的方法
公开(公告)号：US20060256612A1
公开(公告)日：2006-11-16
申请号：US11303910
申请日：2005-12-19
申请人： Beak-hyung Cho , Jong-soo Seo , Du-eung Kim , Woo-yeong Cho
发明人： Beak-hyung Cho , Jong-soo Seo , Du-eung Kim , Woo-yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.
摘要翻译：提供了一种用于驱动相变存储器件的字线的方法和装置。该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

10. 发明授权

US07457151B2 Phase change random access memory (PRAM) device having variable drive voltages 有权
标题翻译：具有可变驱动电压的相变随机存取存储器（PRAM）装置
公开(公告)号：US07457151B2
公开(公告)日：2008-11-25
申请号：US11319601
申请日：2005-12-29
申请人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C5/145 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/009
摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.
摘要翻译：一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。写升压电路响应于第一操作模式中的控制信号而升高第一电压并输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且第三操作模式。写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

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