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1. 发明授权

US07283387B2 Phase change random access memory device having variable drive voltage circuit 有权
标题翻译：具有可变驱动电压电路的相变随机存取存储器件
公开(公告)号：US07283387B2
公开(公告)日：2007-10-16
申请号：US11316256
申请日：2005-12-23
申请人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.
摘要翻译：相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的数据线和将数据线连接到读出放大器单元的控制节点。在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

2. 发明申请

US20070058425A1 Phase change random access memory device having variable drive voltage circuit 有权
公开(公告)号：US20070058425A1
公开(公告)日：2007-03-15
申请号：US11316256
申请日：2005-12-23
申请人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

3. 发明授权

US07688620B2 Nonvolatile memory device and related methods of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07688620B2
公开(公告)日：2010-03-30
申请号：US11834843
申请日：2007-08-07
申请人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
发明人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064
摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.
摘要翻译：在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

4. 发明授权

US07876609B2 Nonvolatile memory device and related methods of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07876609B2
公开(公告)日：2011-01-25
申请号：US12720918
申请日：2010-03-10
申请人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
发明人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064
摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.
摘要翻译：在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

5. 发明授权

US07746688B2 PRAM and method of firing memory cells 有权
标题翻译： PRAM和烧存存储单元的方法
公开(公告)号：US07746688B2
公开(公告)日：2010-06-29
申请号：US11933536
申请日：2007-11-01
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim , Woo-yeong Cho , Chang-han Choi , Ki-won Lim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim , Woo-yeong Cho , Chang-han Choi , Ki-won Lim
IPC分类号： G11C11/00
CPC分类号： G11C8/06 , G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/12005 , G11C29/50 , G11C2013/0083 , G11C2013/0092
摘要： A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher than the first voltage and supplies a firing pulse to at least one firing-failed phase change memory cell.
摘要翻译： PRAM包括相变存储单元的存储单元阵列和接收外部提供的第一电压的写入电路，并且在正常操作模式中提供用于将数据写入存储单元的写入脉冲。写入电路还接收高于第一电压的外部提供的第二电压，并且向至少一个点火故障相变存储单元提供点火脉冲。

6. 发明授权

US07535747B2 Phase change random access memory and related methods of operation 有权
标题翻译：相变随机存取存储器及相关操作方法
公开(公告)号：US07535747B2
公开(公告)日：2009-05-19
申请号：US11844512
申请日：2007-08-24
申请人： Kwang-jin Lee , Woo-yeong Cho
发明人： Kwang-jin Lee , Woo-yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078
摘要： In a phase change random access memory (PRAM) device, data is programmed in selected memory cells using a plurality of program loops. In each program loop, division program operations for cell groups including the selected memory cells are performed in consecutive timeslots.
摘要翻译：在相变随机存取存储器（PRAM）装置中，使用多个程序循环将数据编程在所选存储单元中。在每个程序循环中，在连续的时隙中执行包括所选存储单元的单元组的分割程序操作。

7. 发明授权

US07701757B2 Phase change random access memory device and related methods of operation 有权
标题翻译：相变随机存取存储器件及相关操作方法
公开(公告)号：US07701757B2
公开(公告)日：2010-04-20
申请号：US11834845
申请日：2007-08-07
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of operating a phase change random access memory (PRAM) device comprises performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.
摘要翻译：一种操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选择的PRAM单元中，其中所述程序操作包括多个顺序程序循环。该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

8. 发明授权

US07580295B2 Semiconductor memory device and memory system including semiconductor memory device 有权
标题翻译：半导体存储器件和包括半导体存储器件的存储器系统
公开(公告)号：US07580295B2
公开(公告)日：2009-08-25
申请号：US11850128
申请日：2007-09-05
申请人： Kwang-jin Lee , Woo-yeong Cho , Hye-jin Kim
发明人： Kwang-jin Lee , Woo-yeong Cho , Hye-jin Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/22
摘要： A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.
摘要翻译：半导体存储器件包括包括第一类型存储单元的存储单元阵列。存储单元阵列响应于设计用于包括除了第一类型之外的类型的存储器单元的存储单元阵列的操作的信号执行写入和读取操作。

9. 发明授权

US08320168B2 Phase change random access memory device and related methods of operation 有权
标题翻译：相变随机存取存储器件及相关操作方法
公开(公告)号：US08320168B2
公开(公告)日：2012-11-27
申请号：US13108143
申请日：2011-05-16
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.
摘要翻译：操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

10. 发明申请

US20080084736A1 Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same 有权
标题翻译：多端口相变随机存取存储单元和多端口相变随机存取存储器件包括相同
公开(公告)号：US20080084736A1
公开(公告)日：2008-04-10
申请号：US11902704
申请日：2007-09-25
申请人： Kwang-jin Lee , Du-eung Kim , Chang-soo Lee , Qi Wang
发明人： Kwang-jin Lee , Du-eung Kim , Chang-soo Lee , Qi Wang
IPC分类号： G11C11/00
CPC分类号： G11C8/16 , G11C13/0004 , G11C2213/74 , G11C2213/79
摘要： A multi-port phase change random access memory (PRAM) cell, includes a PRAM element including a phase change material, a writing controller configured to operate in correspondence with a writing word line, the writing controller connecting a writing bit line to the PRAM element, and a reading controller configured to operate in correspondence with a reading word line, the reading controller connecting the PRAM element to a reading bit line.
摘要翻译：多端口相变随机存取存储器（PRAM）单元包括：包括相变材料的PRAM元件，配置成与写入字线对应地进行操作的写入控制器，写入控制器将写入位线连接到PRAM元件以及读取控制器，被配置为与读取字线对应地操作，读取控制器将PRAM元件连接到读取位线。

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