专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070086235A1 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070086235A1
公开(公告)日：2007-04-19
申请号：US11529323
申请日：2006-09-29
申请人： Du-eung Kim , Chang--soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang--soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

2. 发明授权

US07881103B2 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07881103B2
公开(公告)日：2011-02-01
申请号：US12574783
申请日：2009-10-07
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

3. 发明授权

US07450415B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07450415B2
公开(公告)日：2008-11-11
申请号：US11640956
申请日：2006-12-19
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
摘要翻译：提供了相变存储器件。相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

4. 发明申请

US20100019217A1 PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20100019217A1
公开(公告)日：2010-01-28
申请号：US12574783
申请日：2009-10-07
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

5. 发明授权

US07613037B2 Phase-change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07613037B2
公开(公告)日：2009-11-03
申请号：US11529323
申请日：2006-09-29
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Byung-gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1675 , Y10S977/754
摘要： A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.
摘要翻译：相变存储器件包括半导体衬底，布置在半导体衬底上的位线和字线彼此相交的相变存储器件，以及插入位线和字线之间的相变材料带，并且沿相对方向其基本上平行于字线的至少一部分。

6. 发明申请

US20070153616A1 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20070153616A1
公开(公告)日：2007-07-05
申请号：US11640956
申请日：2006-12-19
申请人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
发明人： Du-eung Kim , Chang-soo Lee , Woo-yeong Cho , Beak-hyung Cho , Byung-gil Choi
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
摘要翻译：提供了相变存储器件。相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

7. 发明申请

US20070159878A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20070159878A1
公开(公告)日：2007-07-12
申请号：US11648558
申请日：2007-01-03
申请人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
发明人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
IPC分类号： G11C5/06 , G11C11/00 , G11C8/00
CPC分类号： G11C7/18 , G11C8/12 , G11C13/0004 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
摘要翻译：相变存储器件包括：半导体衬底，其包括多个相变存储器单元;多个局部位线，其延伸在所述半导体衬底上;所述多个局部位线中的每一个耦合到所述多个相变存储器单元; 以及在所述多个局部位线上延伸的多个全局位线，所述多个全局位线中的每一条选择性地耦合到所述多个局部位线。多个全局位线位于半导体衬底上的两个或更多个不同的布线层上。

8. 发明授权

US07405965B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07405965B2
公开(公告)日：2008-07-29
申请号：US11648558
申请日：2007-01-03
申请人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
发明人： Byung-gil Choi , Du-eung Kim , Woo-yeong Cho
IPC分类号： G11C11/22
CPC分类号： G11C7/18 , G11C8/12 , G11C13/0004 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
摘要翻译：相变存储器件包括：半导体衬底，其包括多个相变存储器单元;多个局部位线，其延伸在所述半导体衬底上;所述多个局部位线中的每一个耦合到所述多个相变存储器单元; 以及在所述多个局部位线上延伸的多个全局位线，所述多个全局位线中的每一条选择性地耦合到所述多个局部位线。多个全局位线位于半导体衬底上的两个或更多个不同的布线层上。

9. 发明申请

US20080232177A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20080232177A1
公开(公告)日：2008-09-25
申请号：US12052761
申请日：2008-03-21
申请人： Byung-gil Choi , Du-eung Kim
发明人： Byung-gil Choi , Du-eung Kim
IPC分类号： G11C7/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： Disclosed is a nonvolatile memory device using a variable resistive element, and a data read circuit for use in variable resistive memory devices. More specifically, embodiments of the invention provide a data read circuit with one or more decoupling units to remove noise from one or more corresponding control signals. For instance, embodiments of the invention remove noise from a clamping control signal, a read bias control signal, and/or precharge signal. The disclosed decoupling units may be used alone or in any combination. Embodiments of the invention are beneficial because they can increase sensing margin and improve the reliability of read operations in memory devices with variable resistive elements.
摘要翻译：公开了一种使用可变电阻元件的非易失性存储器件和用于可变电阻存储器件的数据读取电路。更具体地，本发明的实施例提供具有一个或多个去耦单元的数据读取电路，以从一个或多个相应的控制信号中去除噪声。例如，本发明的实施例从钳位控制信号，读取偏置控制信号和/或预充电信号中去除噪声。所公开的去耦单元可以单独使用或以任何组合使用。本发明的实施例是有益的，因为它们可以增加感测裕度并提高具有可变电阻元件的存储器件中的读取操作的可靠性。

10. 发明授权

US07808815B2 Variable resistance memory device and method of manufacturing the same 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US07808815B2
公开(公告)日：2010-10-05
申请号：US11865491
申请日：2007-10-01
申请人： Yu-hwan Ro , Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh
发明人： Yu-hwan Ro , Byung-gil Choi , Woo-yeong Cho , Hyung-rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/00 , G11C13/0004 , G11C2213/72 , H01L27/24 , Y10S977/754
摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.
摘要翻译：一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线形成在全局位线上，均匀分离，并沿第一方向延伸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式