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1. 发明授权

US07514360B2 Thermal robust semiconductor device using HfN as metal gate electrode and the manufacturing process thereof 有权
标题翻译：使用HfN作为金属栅电极的耐热半导体器件及其制造方法
公开(公告)号：US07514360B2
公开(公告)日：2009-04-07
申请号：US10802563
申请日：2004-03-17
申请人： Hong Yu Yu , Ming-Fu Li , Dim-Lee Kwong , Lakshmi Kanta Bera
发明人： Hong Yu Yu , Ming-Fu Li , Dim-Lee Kwong , Lakshmi Kanta Bera
IPC分类号： H01L21/44
CPC分类号： H01L29/4908 , H01L21/28088 , H01L21/823828 , H01L29/4966 , H01L29/51 , H01L29/7833
摘要： This invention relates to a semiconductor device making use of a highly thermal robust metal electrode as gate material. In particular, the development of Hafnium Nitride as a metal gate electrode (or a part of the metal gate stack) is taught and its manufacturing steps of fabrication with different embodiments are shown.
摘要翻译：本发明涉及利用高度耐热的金属电极作为栅极材料的半导体器件。特别地，教导了作为金属栅极电极（或金属栅极叠层的一部分）的氮化铪的开发，并且示出了其具有不同实施例的制造的制造步骤。

2. 发明申请

US20080135949A1 Stacked silicon-germanium nanowire structure and method of forming the same 审中-公开
标题翻译：堆叠硅 - 锗纳米线结构及其形成方法
公开(公告)号：US20080135949A1
公开(公告)日：2008-06-12
申请号：US11636381
申请日：2006-12-08
申请人： Guo Qiang Lo , Lakshmi Kanta Bera , Hoai Son Nguyen , Navab Singh
发明人： Guo Qiang Lo , Lakshmi Kanta Bera , Hoai Son Nguyen , Navab Singh
IPC分类号： H01L29/94
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/42392
摘要： A method of forming a stacked silicon-germanium nanowire structure on a support substrate is disclosed. The method includes forming a stacked structure on the support substrate, the stacked structure comprising at least one channel layer and at least one interchannel layer deposited on the channel layer; forming a fin structure from the stacked structure, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing the fin portion of the fin structure thereby forming the silicon-germanium nanowire being surrounded by a layer of oxide; and removing the layer of oxide to form the silicon-germanium nanowire. A method of forming a gate-all-around transistor comprising forming a stacked silicon-germanium nanowire structure that has been formed on a support substrate is also disclosed. A stacked silicon-germanium nanowire structure and a gate-all-around transistor comprising the stacked silicon-germanium nanowire structure are also disclosed.
摘要翻译：公开了一种在支撑衬底上形成堆叠的硅 - 锗纳米线结构的方法。该方法包括在支撑基板上形成堆叠结构，该堆叠结构包括至少一个沟道层和沉积在沟道层上的至少一个沟道间层; 从所述堆叠结构形成翅片结构，所述翅片结构包括至少两个支撑部分和布置在其间的翅片部分; 氧化翅片结构的翅片部分，从而形成被一层氧化物包围的硅 - 锗纳米线; 并除去氧化物层以形成硅 - 锗纳米线。还公开了一种形成栅极全绕晶体管的方法，包括形成已经形成在支撑衬底上的堆叠的硅 - 锗纳米线结构。还公开了堆叠的硅 - 锗纳米线结构和包括堆叠的硅 - 锗纳米线结构的栅极全绕晶体管。

3. 发明授权

US07397090B2 Gate electrode architecture for improved work function tuning and method of manufacture 失效
标题翻译：栅电极结构，用于改进工作功能调整和制造方法
公开(公告)号：US07397090B2
公开(公告)日：2008-07-08
申请号：US11160126
申请日：2005-06-09
申请人： Shajan Mathew , Lakshmi Kanta Bera , Narayanan Balasubramanian
发明人： Shajan Mathew , Lakshmi Kanta Bera , Narayanan Balasubramanian
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.
摘要翻译：形成具有不同功函数的栅电极的方法包括形成第一导电类型的第一阱和第二导电类型的第二阱。随后，栅极电介质层沉积在第一和第二阱上。包括两个或多个薄金属/金属氮化物层的多层堆叠接着形成在第一阱上。在多层叠层上形成厚金属/金属氮化物层以形成第一栅电极。厚金属/金属氮化物层也形成在在第二阱上延伸的栅极电介质层部分上，从而形成第二栅电极。然后将第一和第二电极退火，然后根据需要显示不同的功函数。

4. 发明申请

US20100052064A1 METHOD FOR STRAINING A SEMICONDUCTOR WAFER AND A WAFER SUBSTRATE UNIT USED THEREIN 审中-公开
标题翻译：用于应变半导体波长的方法和使用它的波导衬底单元
公开(公告)号：US20100052064A1
公开(公告)日：2010-03-04
申请号：US12373881
申请日：2006-07-20
申请人： Guo-Qiang Lo , Lakshmi Kanta Bera , Li-Hui Guo , Wei-Yip Loh , Ebin Liao , Xiaowu Zhang
发明人： Guo-Qiang Lo , Lakshmi Kanta Bera , Li-Hui Guo , Wei-Yip Loh , Ebin Liao , Xiaowu Zhang
IPC分类号： H01L27/092 , H01L21/50
CPC分类号： H01L21/324 , H01L21/823807 , H01L29/6659 , H01L29/7842
摘要： The present invention provides a method for straining a semiconductor wafer, the method comprising: providing a semiconductor wafer, the semiconductor wafer having a first wafer surface and a second wafer surface arranged substantially opposite the first wafer surface; providing a substrate, the substrate having a substrate surface; adhering the first wafer surface to the substrate surface, thereby connecting the semiconductor wafer to the substrate and forming a wafer substrate unit; heating the semiconductor wafer and the substrate to a first temperature; and cooling the wafer substrate unit to a second temperature lower than the first temperature; thereby straining and bending the semiconductor wafer. The present invention further provides a wafer substrate unit.
摘要翻译：本发明提供了一种使半导体晶片变形的方法，所述方法包括：提供半导体晶片，所述半导体晶片具有第一晶片表面和与所述第一晶片表面基本相对的第二晶片表面; 提供衬底，所述衬底具有衬底表面; 将第一晶片表面粘合到基板表面，从而将半导体晶片连接到基板并形成晶片基板单元; 将半导体晶片和衬底加热到第一温度; 以及将所述晶片衬底单元冷却到低于所述第一温度的第二温度; 从而使半导体晶片变形和弯曲。本发明还提供了一种晶片衬底单元。

5. 发明授权

US07439165B2 Method of fabricating tensile strained layers and compressive strain layers for a CMOS device 失效
标题翻译：制造CMOS器件的拉伸应变层和压应变层的方法
公开(公告)号：US07439165B2
公开(公告)日：2008-10-21
申请号：US11100206
申请日：2005-04-06
申请人： Patrick Guo Oiang Lo , Lakshmi Kanta Bera , Wei Yip Loh , Balakumar Subramanian , Narayanan Balasubramanian
发明人： Patrick Guo Oiang Lo , Lakshmi Kanta Bera , Wei Yip Loh , Balakumar Subramanian , Narayanan Balasubramanian
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/66477 , H01L29/66742 , H01L29/78 , H01L29/78687
摘要： A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration.
摘要翻译：已经开发了用于形成拉伸和压缩应变硅层以适应MOSFET或CMOS器件的沟道区的工艺。在形成浅沟槽隔离结构以及施加高温氧化和激活程序之后，开始用于获得应变硅层的制造顺序。沉积半导体合金层，然后沉积氧化工序，将锗组分从上覆的半导体合金层分离成下面的单晶硅体。分离到下面的单晶硅体中的锗的水平决定了随后选择性生长的硅层的拉伸状态的应变水平。本发明的第二个实施方案的特征在于在氧化过程之前使半导体合金层的一部分变薄，允许较低水平的锗分离成下面的单晶硅体的第一下面部分，同时在相同的氧化过程底层单晶硅体的第二部分接受较高水平的锗分离。因此，随后沉积的硅 - 锗层，尽管相同的工艺和厚度，可以根据不同的下层部分的锗浓度在不同的状态（拉伸或压缩）和水平应变。

6. 发明授权

US06716570B2 Low temperature resist trimming process 失效
标题翻译：低温抗蚀剂修剪工艺
公开(公告)号：US06716570B2
公开(公告)日：2004-04-06
申请号：US10154280
申请日：2002-05-23
申请人： Ranganathan Nagarajan , Shajan Mathew , Lakshmi Kanta Bera
发明人： Ranganathan Nagarajan , Shajan Mathew , Lakshmi Kanta Bera
IPC分类号： G03F736
CPC分类号： G03F7/40 , H01L21/28123 , H01L21/3086 , H01L21/3088 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (
摘要翻译：描述了在半导体器件和MEMS器件的集成电路的制造期间修整光致抗蚀剂图案的过程。使用低温（<20℃），高密度氧和氩等离子体和强烈的紫外线辐射的组合来同时修整和硬化ICP腔中的光致抗蚀剂线宽。作为替代，在ICP等离子体蚀刻之前，可以在泛光曝光工具中执行UV硬化步骤。另一个选择是首先进行氩等离子体处理以使抗蚀剂硬化，然后在第二步骤中施加氧等离子体来修整光致抗蚀剂。以可控的方式降低垂直和水平蚀刻速率，这对于在小于100nm的MOS晶体管中产生栅极长度是有用的。该方法还可以用于可控地增加光致抗蚀剂特征中的空间宽度。

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