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1. 发明授权

US06716570B2 Low temperature resist trimming process 失效
标题翻译：低温抗蚀剂修剪工艺
公开(公告)号：US06716570B2
公开(公告)日：2004-04-06
申请号：US10154280
申请日：2002-05-23
申请人： Ranganathan Nagarajan , Shajan Mathew , Lakshmi Kanta Bera
发明人： Ranganathan Nagarajan , Shajan Mathew , Lakshmi Kanta Bera
IPC分类号： G03F736
CPC分类号： G03F7/40 , H01L21/28123 , H01L21/3086 , H01L21/3088 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (
摘要翻译：描述了在半导体器件和MEMS器件的集成电路的制造期间修整光致抗蚀剂图案的过程。使用低温（<20℃），高密度氧和氩等离子体和强烈的紫外线辐射的组合来同时修整和硬化ICP腔中的光致抗蚀剂线宽。作为替代，在ICP等离子体蚀刻之前，可以在泛光曝光工具中执行UV硬化步骤。另一个选择是首先进行氩等离子体处理以使抗蚀剂硬化，然后在第二步骤中施加氧等离子体来修整光致抗蚀剂。以可控的方式降低垂直和水平蚀刻速率，这对于在小于100nm的MOS晶体管中产生栅极长度是有用的。该方法还可以用于可控地增加光致抗蚀剂特征中的空间宽度。

2. 发明授权

US07381629B2 Method of forming through-wafer interconnects for vertical wafer level packaging 失效
标题翻译：形成用于垂直晶片级封装的贯穿晶片互连的方法
公开(公告)号：US07381629B2
公开(公告)日：2008-06-03
申请号：US11705480
申请日：2007-02-12
申请人： Chirayarikathuveedu Premachandran Sankarapillai , Ranganathan Nagarajan , Mohanraj Soundarapandian
发明人： Chirayarikathuveedu Premachandran Sankarapillai , Ranganathan Nagarajan , Mohanraj Soundarapandian
IPC分类号： H01L21/46
CPC分类号： H01L21/76898 , H01L21/6835 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/09701 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.
摘要翻译：提供其上具有目标转印区域的基板。牺牲晶片涂覆有对金属具有低粘附性的聚合物层。将导电层涂覆在聚合物层上并用被图案化以向导电层提供开口的光致抗蚀剂层覆盖。在开口内的导电层上形成薄膜和无源或有源器件结构。衬底被结合到牺牲晶片，其中薄膜和无源或有源器件结构和光致抗蚀剂层提供接合，并且其中薄膜和无源或有源器件结构在目标转移区域接触衬底。光致抗蚀剂在高频搅拌槽中剥离，其中光致抗蚀剂与牺牲晶片分离，其中薄膜和被动或主动器件结构与聚合物层分离以完成转移键合。

3. 发明申请

US20050146049A1 RF and MMIC stackable micro-modules 失效
标题翻译： RF和MMIC可堆叠微型模块
公开(公告)号：US20050146049A1
公开(公告)日：2005-07-07
申请号：US10746199
申请日：2003-12-24
申请人： Vaidyanathan Kripesh , Mihai Rotaru , Ganesh Periasamy , Seung Yoon , Ranganathan Nagarajan
发明人： Vaidyanathan Kripesh , Mihai Rotaru , Ganesh Periasamy , Seung Yoon , Ranganathan Nagarajan
IPC分类号： H01L21/48 , H01L21/8238 , H01L23/498 , H01L23/66 , H01L25/065 , H05K1/02 , H05K1/11
CPC分类号： H01L23/66 , H01L21/486 , H01L23/49827 , H01L25/0657 , H01L25/105 , H01L2223/6622 , H01L2224/16 , H01L2225/1023 , H01L2225/1058 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/0222 , H05K1/115 , H05K2201/0949 , H05K2201/09809 , Y10T29/49117 , Y10T29/49156 , Y10T29/49165
摘要： A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.
摘要翻译：实现了在制造集成电路装置中形成具有微带接地面的屏蔽通孔的新方法。该方法包括：首先提供衬底。蚀刻基板以形成具有微带接地层的规划屏蔽通孔的孔。第一电介质层形成在衬底的顶侧上方并且衬套孔。第一导电层沉积在第一介电层上并衬在孔上。沉积第二介电层，覆盖第一导电层并衬套孔。沉积第二导电层，覆盖第二介电层并填充孔。第二导电层被平坦化以将第二导电层限制在孔中，从而完成具有微带接地平面的屏蔽通孔。使用具有微带接地层的屏蔽通孔形成硅载体模块和堆叠的多个集成电路模块，以改善射频性能。

4. 发明授权

US07682914B2 Fully salicided (FUCA) MOSFET structure 失效
标题翻译：完全水化（FUSA）MOSFET结构
公开(公告)号：US07682914B2
公开(公告)日：2010-03-23
申请号：US11981496
申请日：2007-10-30
申请人： Patrick Guo Qiang Lo , Wei Yip Loh , Ranganathan Nagarajan , Narayanan Balasubramanian
发明人： Patrick Guo Qiang Lo , Wei Yip Loh , Ranganathan Nagarajan , Narayanan Balasubramanian
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , H01L29/458 , H01L29/4908 , H01L29/66643 , H01L29/66772 , H01L29/78636
摘要： A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.
摘要翻译：描述了一种形成具有完全硅化栅电极和完全硅化的凸起S / D元件的MOSFET，该S / D元件几乎共面以在形成与硅化物区域的接触时允许更宽的工艺裕度。在STI区域上形成绝缘体阻挡层，并且在绝缘体阻挡层和有源区上设置诸如Ti / TiN的共形硅化停止层。多晶硅层沉积在硅化终止层上，并通过CMP工艺平坦化以形成凸起的S / D元件。去除栅电极上的氧化物硬掩模以在间隔件之间产生轻微的凹陷。硅化工艺产生栅电极和由NiSi组成的升高的S / D元件。可选地，在绝缘体块掩模和间隔物之间的衬底中形成凹部，并且使用肖特基势垒代替硅化阻挡层以形成肖特基势垒MOSFET。

5. 发明授权

US06573154B1 High aspect ratio trench isolation process for surface micromachined sensors and actuators 失效
标题翻译：表面微加工传感器和执行器的高纵横比沟槽隔离工艺
公开(公告)号：US06573154B1
公开(公告)日：2003-06-03
申请号：US09696082
申请日：2000-10-26
申请人： Uppili Sridhar , Ranganathan Nagarajan , Yu Bo Miao , Yi Su
发明人： Uppili Sridhar , Ranganathan Nagarajan , Yu Bo Miao , Yi Su
IPC分类号： H01L2176
CPC分类号： B81C1/00619
摘要： A process for fabricating an integrated circuit sensor/actuator is described. High aspect ratio deep silicon beams are formed by a process of deep trench etch and silicon undercut release etch by using oxide spacers to protect the silicon beam sidewalls during release etch. An oxide layer is then formed, followed by deposition of a controlled thickness of polysilicon which is then thermally oxidized. The polysilicon layer inside the trenches gets fully oxidized resulting in void-free trench isolation. This process creates a silicon island or beam on three sides leaving the third side for interfacing with the sensor/actuator beams. The sensor/actuator is formed by a similar process of deep trench etch and release etch process on the same substrate. These suspended beams of the sensors and actuators are bridged with the silicon islands from the fourth side. The above process finally results in suspended silicon beams connected to electrically isolated silicon islands.
摘要翻译：描述了一种用于制造集成电路传感器/致动器的工艺。通过使用氧化物间隔物的深沟槽蚀刻和硅蚀刻蚀刻蚀刻的工艺形成高纵横比深硅光束，以在释放蚀刻期间保护硅束侧壁。然后形成氧化物层，然后沉积受控厚度的多晶硅，然后热氧化。沟槽内的多晶硅层被完全氧化，导致无空隙的沟槽隔离。该过程在三侧产生硅岛或光束，离开第三侧以与传感器/致动器光束接口。传感器/致动器通过在同一衬底上的深沟槽蚀刻和释放蚀刻工艺的类似工艺形成。这些传感器和致动器的悬挂梁与第四侧的硅岛桥接。上述过程最终导致连接到电隔离硅岛的悬浮硅束。

6. 发明授权

US06461888B1 Lateral polysilicon beam process 失效
标题翻译：横向多晶硅束工艺
公开(公告)号：US06461888B1
公开(公告)日：2002-10-08
申请号：US09880249
申请日：2001-06-14
申请人： Uppili Sridhar , Ranganathan Nagarajan , Yubo Miao
发明人： Uppili Sridhar , Ranganathan Nagarajan , Yubo Miao
IPC分类号： H01L2100
CPC分类号： B81C1/0015 , B81B2203/0136
摘要： A process has been described which makes use of polysilicon beam as the structural material instead of single crystal silicon for the fabrication of MEMS sensors/actuators. The invention describes the process for fabricating suspended polysilicon beams by using deep trenches etched into silicon substrate as a kind of a mould to form polysilicon beams. The polysilicon beams are subsequently released by isotropically etching away the silicon surrounding the polysilicon beams. This results in free standing polysilicon members, which form the MEMS structures. In addition to the general process, three approaches to making electrical contact to the beams are presented.
摘要翻译：已经描述了使用多晶硅束作为结构材料而不是用于制造MEMS传感器/致动器的单晶硅的方法。本发明描述了通过使用蚀刻到硅衬底中的深沟槽作为一种模具来形成多晶硅束来制造悬浮多晶硅束的工艺。随后通过各向同性蚀刻掉多晶硅束周围的硅来释放多晶硅束。这导致形成MEMS结构的自由多晶硅构件。除了一般的过程之外，还提出了三种与光束接触的方法。

7. 发明授权

US07183176B2 Method of forming through-wafer interconnects for vertical wafer level packaging 失效
标题翻译：形成用于垂直晶片级封装的贯穿晶片互连的方法
公开(公告)号：US07183176B2
公开(公告)日：2007-02-27
申请号：US10925683
申请日：2004-08-25
申请人： Chirayarikathuveedu Premachandran Sankarapillai , Ranganathan Nagarajan , Mohanraj Soundarapandian
发明人： Chirayarikathuveedu Premachandran Sankarapillai , Ranganathan Nagarajan , Mohanraj Soundarapandian
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76898 , H01L21/6835 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/09701 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.
摘要翻译：在其中设置有通孔的晶片以通过晶片形成通孔。提供牺牲晶片的基板。基材涂覆有对金属具有低粘附性的聚合物。导电层沉积在聚合物上。光致抗蚀剂层涂覆在导电层上。通孔通孔晶片被结合到牺牲晶片，其中光致抗蚀剂层提供接合。暴露在通孔中的光致抗蚀剂被开发出来以露出导电层。通过电镀导电层，用导电材料填充通孔。光致抗蚀剂在超声波浴中剥离，其中光致抗蚀剂与通孔晶片分离，并且其中填充的通孔在聚合物和导电层之间的界面处与聚合物分离，以完成通孔从晶片的分离牺牲晶片。

8. 发明申请

US20060057836A1 Method of stacking thin substrates by transfer bonding 失效
标题翻译：通过转移粘合堆叠薄基板的方法
公开(公告)号：US20060057836A1
公开(公告)日：2006-03-16
申请号：US11169907
申请日：2005-06-29
申请人： Ranganathan Nagarajan , Chirayarikathuveedu Sankarapillai
发明人： Ranganathan Nagarajan , Chirayarikathuveedu Sankarapillai
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/30
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/05 , H01L24/12 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/13009 , H01L2224/13099 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/07802 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/05552
摘要： This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on a wiring layer interconnecting the subjacent semiconductive devices. The remaining integrated circuit layers are formed by first processing a standard wafer to form integrated circuit devices and wiring levels up to but not including bond pads. Each of these wafers is mounted onto a handler wafer by its upper face with a sacrificial bonding agent. The wafer is thinned, permanently fastened to the top surface of the first base wafer by a non-conductive adhesive applied to the thinned under face, and dismounted from the handler. Vertical openings are etched through the thinned layer to the bond pads on the subjacent wafer. Robust conductive pass-through plugs with integrated upper bond pads are formed in the openings. Additional thinned integrated circuit layers may be prepared, thinned, cemented onto the stack. Wiring interconnections can be made between any two or more layers. The process is unique in that it can be used to further stack and interconnect any number of thinned wafer layers to form a three dimensional integrated circuits, including MEMS devices. This approach provides a low temperature wafer bonding method using an adhesive which results in process simplicity and cost effectiveness by eliminating an additional masking and patterning process for under bump metal thereby enabling standard wafers to be integrated into a 3D stack with existing wire bonded wafers.
摘要翻译：本发明描述了一种堆叠，结合和电互连多个薄集成电路晶片以形成互连的集成电路层的叠层的方法。第一集成电路层通过在硅晶片上的常规处理形成到在互连下面的半导体器件的布线层上图案化接合焊盘的阶段。剩余的集成电路层通过首先处理标准晶片形成集成电路器件和直到但不包括接合焊盘的布线级来形成。这些晶片中的每一个通过其上表面用牺牲粘合剂安装到处理器晶片上。晶片变薄，通过施加到减薄的底面上的非导电粘合剂永久地固定到第一基底晶片的顶表面，并从处理器中卸下。垂直开口通过薄化层蚀刻到相邻晶片上的接合焊盘。在开口中形成具有集成的上接合焊盘的坚固的导电贯穿塞。另外的薄化集成电路层可以被制备，变薄，胶合到堆叠上。可以在任意两层或更多层之间进行布线互连。该方法是独特的，因为其可以用于进一步堆叠和互连任何数量的薄化晶片层，以形成包括MEMS器件的三维集成电路。该方法提供使用粘合剂的低温晶片接合方法，其通过消除用于凸块下金属的附加掩模和图案化工艺而导致工艺简单性和成本效益，从而使标准晶片能够与现有的线接合晶片集成到3D堆叠中。

9. 发明授权

US06787456B1 Wafer-level inter-connector formation method 失效
标题翻译：晶圆级互连器形成方法
公开(公告)号：US06787456B1
公开(公告)日：2004-09-07
申请号：US10392084
申请日：2003-03-20
申请人： Vaidyanathan Kripesh , Mahadevan K Iyer , Ranganathan Nagarajan
发明人： Vaidyanathan Kripesh , Mahadevan K Iyer , Ranganathan Nagarajan
IPC分类号： H01L214763
CPC分类号： H01L21/4853
摘要： Inter-connectors are typically used for interconnecting electronic components. Interconnections between electronic components are generally classified into at least two broad categories of “relatively permanent” and “readily demountable”. A “readily demountable” connector includes a spring-like contact structure of one electronic component for connecting to a terminal of another electronic component. The spring-like contact structure, also known as an inter-connector, generally requires a certain amount of contact force to effect reliable pressure contact to a terminal of an electronic component. Therefore, the shape and metallurgy of the inter-connector are important factors in determining the effectiveness of the inter-connector for making pressure connection to a terminal of the electronic component. Conventional methods of making such an inter-connector use lithographic and planarisation methods to “make” the inter-connectors in segments. This results in the inter-connector segments having joints therebetween. Metallurgically, the joint stress due to joining a pair of inter-connector segments and stress concentration at the joints due forces applied to the inter-connector can lead to the mechanical failure of the inter-connector in Mathieu. An embodiment of the invention uses lithographic techniques and heat treatment methods for forming a structure channel defining the shape and dimension of an inter-connector. The structure channel is then used to “mold” a reproduction of the inter-connector having a single continuous physical segment.
摘要翻译：互连器件通常用于互连电子部件。电子部件之间的互连通常分为至少两大类“相对永久”和“易拆卸”。 “易拆卸”连接器包括用于连接到另一电子部件的端子的一个电子部件的弹簧状接触结构。也称为相互连接器的弹簧状接触结构通常需要一定量的接触力来实现与电子部件的端子的可靠的压力接触。因此，连接器的形状和冶金是确定用于与电子部件的端子进行压力连接的连接器的有效性的重要因素。制造这种连接器的常规方法使用光刻和平面化方法来“制造”分段中的连接器。这导致连接件之间具有接头。在冶金方面，由于连接一对连接器间部分而引起的接头应力和施加在连接器上的接头应力集中会导致Mathieu中连接器的机械故障。本发明的实施例使用光刻技术和热处理方法来形成限定连接器的形状和尺寸的结构通道。然后，结构通道用于“模制”具有单个连续物理段的连接器的再现。

10. 发明授权

US06662654B2 Z-axis accelerometer 失效
公开(公告)号：US06662654B2
公开(公告)日：2003-12-16
申请号：US10409421
申请日：2003-04-08
申请人： Yubo Miao , Ranganathan Nagarajan , Uppili Sridhar , Rakesh Kumar , Qinxin Zhang
发明人： Yubo Miao , Ranganathan Nagarajan , Uppili Sridhar , Rakesh Kumar , Qinxin Zhang
IPC分类号： G01P1500
CPC分类号： G01P15/125 , B81B3/0051 , B81B2201/0235 , B81B2203/053 , G01P15/0802 , G01P2015/0814 , Y10T29/49005
摘要： An accelerometer design is described. It operates by measuring a change in capacitance when one plate is fixed and one is mobile (free to accelerate). Unlike prior art designs where such changes are caused by variations in the plate separation distance, in the design of the present invention the plate separation distance is fixed, it being the effective plate area that changes with acceleration. A key feature is that the basic unit is a pair of capacitors. The fixed plates in each case are at the same relative height but the mobile plates are offset relative to the fixed plates, one mobile plate somewhat higher than its fixed plate with the other mobile plate being somewhat lower. Then, when the mobile plates move (in the same direction), one capacitor increases in value while the other decreases by the same amount. This differential design renders the device insensitive to sources of systematic error such as temperature changes. A process for manufacturing the design is described.

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