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1. 发明授权

US07439165B2 Method of fabricating tensile strained layers and compressive strain layers for a CMOS device 失效
标题翻译：制造CMOS器件的拉伸应变层和压应变层的方法
公开(公告)号：US07439165B2
公开(公告)日：2008-10-21
申请号：US11100206
申请日：2005-04-06
申请人： Patrick Guo Oiang Lo , Lakshmi Kanta Bera , Wei Yip Loh , Balakumar Subramanian , Narayanan Balasubramanian
发明人： Patrick Guo Oiang Lo , Lakshmi Kanta Bera , Wei Yip Loh , Balakumar Subramanian , Narayanan Balasubramanian
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/66477 , H01L29/66742 , H01L29/78 , H01L29/78687
摘要： A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration.
摘要翻译：已经开发了用于形成拉伸和压缩应变硅层以适应MOSFET或CMOS器件的沟道区的工艺。在形成浅沟槽隔离结构以及施加高温氧化和激活程序之后，开始用于获得应变硅层的制造顺序。沉积半导体合金层，然后沉积氧化工序，将锗组分从上覆的半导体合金层分离成下面的单晶硅体。分离到下面的单晶硅体中的锗的水平决定了随后选择性生长的硅层的拉伸状态的应变水平。本发明的第二个实施方案的特征在于在氧化过程之前使半导体合金层的一部分变薄，允许较低水平的锗分离成下面的单晶硅体的第一下面部分，同时在相同的氧化过程底层单晶硅体的第二部分接受较高水平的锗分离。因此，随后沉积的硅 - 锗层，尽管相同的工艺和厚度，可以根据不同的下层部分的锗浓度在不同的状态（拉伸或压缩）和水平应变。

2. 发明授权

US07682914B2 Fully salicided (FUCA) MOSFET structure 失效
标题翻译：完全水化（FUSA）MOSFET结构
公开(公告)号：US07682914B2
公开(公告)日：2010-03-23
申请号：US11981496
申请日：2007-10-30
申请人： Patrick Guo Qiang Lo , Wei Yip Loh , Ranganathan Nagarajan , Narayanan Balasubramanian
发明人： Patrick Guo Qiang Lo , Wei Yip Loh , Ranganathan Nagarajan , Narayanan Balasubramanian
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , H01L29/458 , H01L29/4908 , H01L29/66643 , H01L29/66772 , H01L29/78636
摘要： A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.
摘要翻译：描述了一种形成具有完全硅化栅电极和完全硅化的凸起S / D元件的MOSFET，该S / D元件几乎共面以在形成与硅化物区域的接触时允许更宽的工艺裕度。在STI区域上形成绝缘体阻挡层，并且在绝缘体阻挡层和有源区上设置诸如Ti / TiN的共形硅化停止层。多晶硅层沉积在硅化终止层上，并通过CMP工艺平坦化以形成凸起的S / D元件。去除栅电极上的氧化物硬掩模以在间隔件之间产生轻微的凹陷。硅化工艺产生栅电极和由NiSi组成的升高的S / D元件。可选地，在绝缘体块掩模和间隔物之间的衬底中形成凹部，并且使用肖特基势垒代替硅化阻挡层以形成肖特基势垒MOSFET。

3. 发明授权

US07294890B2 Fully salicided (FUSA) MOSFET structure 失效
标题翻译：完全水化（FUSA）MOSFET结构
公开(公告)号：US07294890B2
公开(公告)日：2007-11-13
申请号：US11071768
申请日：2005-03-03
申请人： Patrick Guo Qiang Lo , Wei Yip Loh , Ranganathan Nagarajan , Narayanan Balasubramanian
发明人： Patrick Guo Qiang Lo , Wei Yip Loh , Ranganathan Nagarajan , Narayanan Balasubramanian
IPC分类号： H01L29/76
CPC分类号： H01L29/78621 , H01L29/458 , H01L29/4908 , H01L29/66643 , H01L29/66772 , H01L29/78636
摘要： A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.
摘要翻译：描述了一种形成具有完全硅化栅电极和完全硅化的凸起S / D元件的MOSFET，该S / D元件几乎共面以在形成与硅化物区域的接触时允许更宽的工艺裕度。在STI区域上形成绝缘体阻挡层，并且在绝缘体阻挡层和有源区上设置诸如Ti / TiN的共形硅化停止层。多晶硅层沉积在硅化终止层上，并通过CMP工艺平坦化以形成凸起的S / D元件。去除栅电极上的氧化物硬掩模以在间隔件之间产生轻微的凹陷。硅化工艺产生栅电极和由NiSi组成的升高的S / D元件。可选地，在绝缘体块掩模和间隔物之间的衬底中形成凹部，并且使用肖特基势垒代替硅化阻挡层以形成肖特基势垒MOSFET。

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