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1. 发明授权

US06933158B1 Method of monitoring anneal processes using scatterometry, and system for performing same 失效
标题翻译：使用散射法监测退火处理的方法，以及执行相同的系统
公开(公告)号：US06933158B1
公开(公告)日：2005-08-23
申请号：US10285041
申请日：2002-10-31
申请人： Kevin R. Lensing , James Broc Stirton , Homi E. Nariman , Steven P. Reeves
发明人： Kevin R. Lensing , James Broc Stirton , Homi E. Nariman , Steven P. Reeves
IPC分类号： G01N21/21 , G01N21/47 , H01L21/265 , H01L21/324 , H01L21/66 , H01L23/544
CPC分类号： G01N21/4788 , G01N21/211 , H01L21/26513 , H01L21/324 , H01L22/20 , H01L22/34
摘要： The present invention is directed to several inventive methods of monitoring anneal processes performed on implant regions, and a system for accomplishing same. In one aspect, the method comprises forming a first plurality of implant regions in a semiconducting substrate, performing at least one anneal process on implant regions, performing a scatterometric measurement of at least one of the implant regions after at least a portion of the anneal process is performed to determine a profile of the implant region and determining an effectiveness of the anneal process based upon the determined profile of the implant region. In other embodiments, one or more parameters of the anneal process may be varied on subsequently processed substrates based upon the determined efficiency of the anneal process.
摘要翻译：本发明涉及用于监测在植入区域上执行的退火处理的几种发明方法，以及用于实现其的系统。在一个方面，该方法包括在半导体衬底中形成第一多个注入区域，在注入区域上执行至少一个退火工艺，在退火工艺的至少一部分之后执行至少一个注入区域的散射测量被执行以确定植入区域的轮廓并且基于所确定的植入区域的轮廓来确定退火过程的有效性。在其他实施例中，退火工艺的一个或多个参数可以基于确定的退火工艺的效率在随后处理的衬底上变化。

2. 发明授权

US06927080B1 Structures for analyzing electromigration, and methods of using same 失效
标题翻译：用于分析电迁移的结构及其使用方法
公开(公告)号：US06927080B1
公开(公告)日：2005-08-09
申请号：US10281760
申请日：2002-10-28
申请人： Homi E. Nariman , James Broc Stirton , Kevin R. Lensing , Steven P. Reeves
发明人： Homi E. Nariman , James Broc Stirton , Kevin R. Lensing , Steven P. Reeves
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , G01R31/2858
摘要： The present invention is generally directed to various structures for analyzing electromigration, and methods of using same. In one illustrative embodiment, the method includes forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive features, forcing an electrical current through at least one of the conductive features until a resistance of the conductive feature increases by a preselected amount, and performing at least one scatterometric measurement of the conductive feature to determine a critical dimension of the conductive feature. In another illustrative embodiment, the method includes forming a plurality of grating structures above a semiconducting substrate, each of the grating structures being comprised of a plurality of conductive features having the same critical dimension, the critical dimension of the features of each of the plurality of grating structures being different, and forcing an electrical current through at least one of the conductive features in each of the plurality of grating structures until a resistance of the conductive feature increases by a preselected amount.
摘要翻译：本发明一般涉及用于分析电迁移的各种结构及其使用方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成光栅结构，该光栅结构由多个导电特征组成，迫使电流通过至少一个导电特征直到导电特征的电阻增加预选量，以及执行导电特征的至少一个散射测量以确定导电特征的临界尺寸。在另一说明性实施例中，该方法包括在半导体衬底之上形成多个光栅结构，每个光栅结构由具有相同临界尺寸的多个导电特征组成，多个光栅结构不同，并且迫使电流通过多个光栅结构中的每一个中的导电特征中的至少一个，直到导电特征的电阻增加预选量。

3. 发明授权

US06881594B1 Method of using scatterometry for analysis of electromigration, and structures for performing same 失效
标题翻译：使用散射法分析电迁移的方法，以及执行相同的结构
公开(公告)号：US06881594B1
公开(公告)日：2005-04-19
申请号：US10281666
申请日：2002-10-28
申请人： James Broc Stirton , Steven P. Reeves , Homi E. Nariman , Kevin R. Lensing
发明人： James Broc Stirton , Steven P. Reeves , Homi E. Nariman , Kevin R. Lensing
IPC分类号： G01N21/17 , G01N21/47 , H01L21/00
CPC分类号： G01N21/47 , G01N21/1717 , G01N2021/1721
摘要： The present invention is generally directed to various methods of using scatterometry for analysis of electromigration. In one illustrative embodiment, the method comprises forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive structures, forcing an electrical current through at least one of the conductive structures and performing scatterometric measurements of at least one conductive structure to detect a change in shape of at least a portion of the conductive structure. In further embodiments, the method comprises determining a susceptibility of at least one conductive structure to electromigration based upon the detected change in shape of the conductive structure.
摘要翻译：本发明一般涉及使用散射法分析电迁移的各种方法。在一个说明性实施例中，该方法包括在半导体衬底上形成光栅结构，该光栅结构由多个导电结构组成，迫使电流通过至少一个导电结构并执行至少一个导电的散射测量结构以检测导电结构的至少一部分的形状变化。在另外的实施例中，该方法包括基于检测到的导电结构的形状的变化来确定至少一个导电结构对电迁移的敏感性。

4. 发明授权

US06660543B1 Method of measuring implant profiles using scatterometric techniques wherein dispersion coefficients are varied based upon depth 有权
标题翻译：使用散射测量技术测量植入物轮廓的方法，其中色散系数基于深度而变化
公开(公告)号：US06660543B1
公开(公告)日：2003-12-09
申请号：US10284996
申请日：2002-10-31
申请人： James Broc Stirton , Kevin R. Lensing , Homi E. Nariman , Steven P. Reeves
发明人： James Broc Stirton , Kevin R. Lensing , Homi E. Nariman , Steven P. Reeves
IPC分类号： H01L2166
CPC分类号： G01N21/4788 , H01J2237/31705 , H01L22/34
摘要： The present invention is directed to several inventive methods for characterizing implant profiles. In one embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating at least one profile trace corresponding,to an anticipated profile of the implant region, wherein, in creating the profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to at least one created profile trace.
摘要翻译：本发明涉及用于表征植入物轮廓的若干发明方法。在一个实施例中，该方法包括提供半导体衬底，在衬底中形成第一多个植入区域，以及在散射测量工具中用光源照射第一组多个植入区域中的至少一个，其中散射仪工具产生轮廓迹线对应于照射的植入区域的植入物轮廓。所述方法还包括产生与植入区域的预期轮廓对应的至少一个轮廓轨迹，其中在产生轮廓轨迹时，折射率（n）和介电常数（k）中的至少一个的值为变化，并将生成的简档跟踪与至少一个创建的简档跟踪进行比较。

5. 发明授权

US06972853B1 Methods of calibrating and controlling stepper exposure processes and tools, and system for accomplishing same 有权
标题翻译：校准和控制步进曝光过程和工具的方法，以及完成相同的系统
公开(公告)号：US06972853B1
公开(公告)日：2005-12-06
申请号：US10259044
申请日：2002-09-27
申请人： James Broc Stirton , Homi E. Nariman
发明人： James Broc Stirton , Homi E. Nariman
IPC分类号： G01B11/28 , G01N21/47 , G01N21/95 , G01N21/956 , G03F7/20 , H01L21/66 , G03K7/23
CPC分类号： G03F7/70625 , G01N21/47 , G01N21/9501 , G01N21/956 , G03F7/70483 , G03F7/70533 , H01L22/12
摘要： The present invention is generally directed to various methods of stepper exposure processes and tools, and system for accomplishing same. In one embodiment, the method comprises forming a grating structure comprised of a plurality of photoresist features above a semiconducting substrate, measuring at least one characteristic of at least one of the photoresist features at a plurality of locations within the grating structure, and determining if the measured characteristic of the photoresist features varies across the grating structure.
摘要翻译：本发明一般涉及步进曝光工艺和工具的各种方法，以及用于实现其的系统。在一个实施例中，该方法包括形成由半导体衬底上方的多个光致抗蚀剂特征构成的光栅结构，测量光栅结构内的多个位置处的至少一个光致抗蚀剂特征的至少一个特性，以及确定是否光刻胶特征的测量特性在光栅结构上变化。

6. 发明授权

US6096643A Method of fabricating a semiconductor device having polysilicon line with extended silicide layer 失效
标题翻译：制造具有多晶硅线的半导体器件的方法，该多晶硅线具有延伸的硅化物层
公开(公告)号：US6096643A
公开(公告)日：2000-08-01
申请号：US164956
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76885 , H01L21/76889 , H01L21/76895
摘要： A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.
摘要翻译：提供了半导体器件和制造工艺，其中多晶硅线路设置在半导体器件的衬底上。多晶硅线可以例如是栅电极。电介质层设置在多晶硅线附近并且在多晶硅线上形成延伸的硅化物层。可以通过在多晶硅线上形成图案化的金属层，在图案化的金属层上形成多晶硅层，并使图案化的金属层与多晶硅层反应以在多晶硅线上形成延伸的硅化物层来形成延伸的硅化物层。器件还可以包括第二多晶硅线，例如栅电极，并且硅化物层可以在第二多晶硅线的顶部上延伸并互连两个多晶硅线。

7. 发明授权

US06791697B1 Scatterometry structure with embedded ring oscillator, and methods of using same 有权
标题翻译：嵌入式环形振荡器的散射结构及其使用方法
公开(公告)号：US06791697B1
公开(公告)日：2004-09-14
申请号：US10104675
申请日：2002-03-21
申请人： Homi E. Nariman
发明人： Homi E. Nariman
IPC分类号： G01B1114
CPC分类号： H01L22/34 , G01R31/2656 , H01L2924/0002 , H01L2924/00
摘要： In one illustrative embodiment, the method involves forming a ring oscillator that includes a first grating structure comprised of a plurality of gate electrode structures for a plurality of N-channel transistors and a second grating structure comprised of a plurality of gate electrode structures for a plurality of P-channel transistors, and measuring the critical dimension and/or profile of at least one of the gate electrode structures in the first grating structure and/or the second grating structure using a scatterometry tool. In another embodiment, the method further involves forming at least one capacitance loading structure, comprised of a plurality of features, as a portion of the ring oscillator, and measuring the critical dimension and/or profile of at least one of the features of the capacitance loading structure using a scatterometry tool.
摘要翻译：在一个说明性实施例中，该方法包括形成环形振荡器，该环形振荡器包括由用于多个N沟道晶体管的多个栅电极结构构成的第一光栅结构，以及由多个用于多个N沟道晶体管的多个栅电极结构的P沟道晶体管，并且使用散射测量工具测量第一光栅结构和/或第二光栅结构中的至少一个栅电极结构的临界尺寸和/或轮廓。在另一个实施例中，该方法还包括形成至少一个由多个特征组成的电容加载结构，作为环形振荡器的一部分，以及测量电容的至少一个特征的临界尺寸和/或轮廓使用散点测量工具加载结构。

8. 发明授权

US06249032B1 Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof 有权
标题翻译：具有多晶硅线上的图案化金属层的半导体器件及其制造方法
公开(公告)号：US06249032B1
公开(公告)日：2001-06-19
申请号：US09165051
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L2941
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).
摘要翻译：提供半导体器件和制造工艺，其中在多晶硅线上形成图案化的金属层。多晶硅线路设置在基板上，并且可以例如是栅电极。介电层设置在多晶硅线附近并且在多晶硅线上形成图案化的金属层。该器件还可以包括第二多晶硅线，例如栅电极，并且图案化的金属层可以在第二多晶硅线的顶部上延伸并互连两个多晶硅线。用于多晶硅线的触点耦合到图案化的金属层。使用图案化金属线可以为接触提供更大的覆盖，然后是下面的多晶硅线，并且可以降低对多晶硅线的薄层电阻。

9. 发明授权

US6146952A Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof 有权
标题翻译：具有自对准不对称源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US6146952A
公开(公告)日：2000-11-14
申请号：US164836
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/42376 , H01L29/7835 , H01L29/665
摘要： A semiconductor device and manufacturing method is provided in which asymmetric source/drain regions are formed using a self aligning implant mask. A gate electrode is formed on a substrate and a dielectric layer is formed over the substrate and adjacent the gate electrode. A masking layer is formed over the dielectric layer and the gate electrode and selectively removed to form an implant mask. The implant mask extends further over a first side of the gate electrode than a second side of the gate electrode. Using the implant mask for alignment, a dopant is implanted into the active regions of the substrate adjacent the gate electrode to form a first heavily-doped region adjacent the first side of the gate electrode and second heavily-doped region adjacent the second side of the gate electrode. The first heavily-doped region is spaced further from the gate electrode than the second heavily-doped region. Contacts may be formed to the masking layer or a silicide layer formed from the masking layer.
摘要翻译：提供一种半导体器件和制造方法，其中使用自对准注入掩模形成不对称的源极/漏极区域。在基板上形成栅电极，在基板上形成电介质层，与栅电极相邻。在电介质层和栅电极之上形成掩模层，并选择性地去除以形成植入物掩模。植入掩模在栅电极的第一侧上比栅电极的第二侧进一步延伸。使用注入掩模进行对准，将掺杂剂注入与栅电极相邻的衬底的有源区中，以形成与栅电极的第一侧相邻的第一重掺杂区和与第二重掺杂区相邻的第二重掺杂区栅电极。第一重掺杂区域比栅极电极比第二重掺杂区域更远。可以将掩模层或由掩模层形成的硅化物层形成触点。

10. 发明授权

US06767835B1 Method of making a shaped gate electrode structure, and device comprising same 有权
标题翻译：制造成形栅电极结构的方法及其制造方法
公开(公告)号：US06767835B1
公开(公告)日：2004-07-27
申请号：US10135616
申请日：2002-04-30
申请人： Homi E. Nariman , David E. Brown
发明人： Homi E. Nariman , David E. Brown
IPC分类号： H01L21302
CPC分类号： H01L29/66507 , H01L21/28114 , H01L21/823456 , H01L21/82385
摘要： In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure. In another illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a first layer of polysilicon above the gate insulation layer, implanting a dopant material into the first layer of polysilicon to form a doped region having a dopant concentration level in the layer of polysilicon, forming a second layer of polysilicon above the doped region of the first layer of polysilicon, the second layer of polysilicon having a dopant concentration level that is less than the dopant concentration level of the doped region in the first layer of polysilircon, and performing an etching process on the second layer of polysilicon and the doped region in the first layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode.
摘要翻译：在一个说明性实施例中，该方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上方形成多晶硅层，将掺杂剂材料注入到多晶硅层中，在多晶硅掺杂层上形成未掺杂的多晶硅层以及对所述多晶硅的未掺杂层和所述多晶硅的掺杂层进行蚀刻处理以限定在上表面处的宽度大于所述栅电极的基极处的栅电极的宽度的栅电极。在另外的实施例中，该方法包括在栅电极上形成难熔金属层，并进行至少一个加热工艺，以在栅电极结构上形成金属硅化物区。在另一说明性实施例中，该方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上方形成第一层多晶硅，将掺杂剂材料注入到第一多晶硅层中以形成掺杂浓度水平的掺杂区域所述多晶硅层在所述第一多晶硅层的掺杂区域的上方形成第二多晶硅层，所述第二层多晶硅的掺杂浓度水平小于所述第一层聚硅氧烷中的掺杂区域的掺杂浓度水平并且对所述第二多晶硅层和所述第一多晶硅层中的掺杂区域进行蚀刻处理以限定在上表面处的宽度大于所述栅极的基极处的栅电极的宽度的栅电极电极。

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