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1. 发明授权

US6096643A Method of fabricating a semiconductor device having polysilicon line with extended silicide layer 失效
标题翻译：制造具有多晶硅线的半导体器件的方法，该多晶硅线具有延伸的硅化物层
公开(公告)号：US6096643A
公开(公告)日：2000-08-01
申请号：US164956
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76885 , H01L21/76889 , H01L21/76895
摘要： A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.
摘要翻译：提供了半导体器件和制造工艺，其中多晶硅线路设置在半导体器件的衬底上。多晶硅线可以例如是栅电极。电介质层设置在多晶硅线附近并且在多晶硅线上形成延伸的硅化物层。可以通过在多晶硅线上形成图案化的金属层，在图案化的金属层上形成多晶硅层，并使图案化的金属层与多晶硅层反应以在多晶硅线上形成延伸的硅化物层来形成延伸的硅化物层。器件还可以包括第二多晶硅线，例如栅电极，并且硅化物层可以在第二多晶硅线的顶部上延伸并互连两个多晶硅线。

2. 发明授权

US06249032B1 Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof 有权
标题翻译：具有多晶硅线上的图案化金属层的半导体器件及其制造方法
公开(公告)号：US06249032B1
公开(公告)日：2001-06-19
申请号：US09165051
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L2941
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).
摘要翻译：提供半导体器件和制造工艺，其中在多晶硅线上形成图案化的金属层。多晶硅线路设置在基板上，并且可以例如是栅电极。介电层设置在多晶硅线附近并且在多晶硅线上形成图案化的金属层。该器件还可以包括第二多晶硅线，例如栅电极，并且图案化的金属层可以在第二多晶硅线的顶部上延伸并互连两个多晶硅线。用于多晶硅线的触点耦合到图案化的金属层。使用图案化金属线可以为接触提供更大的覆盖，然后是下面的多晶硅线，并且可以降低对多晶硅线的薄层电阻。

3. 发明授权

US6146952A Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof 有权
标题翻译：具有自对准不对称源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US6146952A
公开(公告)日：2000-11-14
申请号：US164836
申请日：1998-10-01
申请人： Homi E. Nariman , H. Jim Fulford , Charles E. May
发明人： Homi E. Nariman , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/42376 , H01L29/7835 , H01L29/665
摘要： A semiconductor device and manufacturing method is provided in which asymmetric source/drain regions are formed using a self aligning implant mask. A gate electrode is formed on a substrate and a dielectric layer is formed over the substrate and adjacent the gate electrode. A masking layer is formed over the dielectric layer and the gate electrode and selectively removed to form an implant mask. The implant mask extends further over a first side of the gate electrode than a second side of the gate electrode. Using the implant mask for alignment, a dopant is implanted into the active regions of the substrate adjacent the gate electrode to form a first heavily-doped region adjacent the first side of the gate electrode and second heavily-doped region adjacent the second side of the gate electrode. The first heavily-doped region is spaced further from the gate electrode than the second heavily-doped region. Contacts may be formed to the masking layer or a silicide layer formed from the masking layer.
摘要翻译：提供一种半导体器件和制造方法，其中使用自对准注入掩模形成不对称的源极/漏极区域。在基板上形成栅电极，在基板上形成电介质层，与栅电极相邻。在电介质层和栅电极之上形成掩模层，并选择性地去除以形成植入物掩模。植入掩模在栅电极的第一侧上比栅电极的第二侧进一步延伸。使用注入掩模进行对准，将掺杂剂注入与栅电极相邻的衬底的有源区中，以形成与栅电极的第一侧相邻的第一重掺杂区和与第二重掺杂区相邻的第二重掺杂区栅电极。第一重掺杂区域比栅极电极比第二重掺杂区域更远。可以将掩模层或由掩模层形成的硅化物层形成触点。

4. 发明授权

US06362510B1 Semiconductor topography having improved active device isolation and reduced dopant migration 有权
标题翻译：半导体形貌具有改进的有源器件隔离和减少掺杂剂迁移
公开(公告)号：US06362510B1
公开(公告)日：2002-03-26
申请号：US09206550
申请日：1998-12-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2822 , H01L21/762 , H01L29/1083 , H01L29/36 , H01L29/518 , H01L29/6659 , H01L29/66651
摘要： A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.
摘要翻译：提出一种用于制造集成电路的方法，其中提供了在其上表面上形成有电介质层的半导体衬底。在从半导体衬底的上表面延伸到电介质层的上表面的电介质层中形成凹槽。然后在沟槽内生长硅外延层。阻挡原子与外延生长工艺同时并入硅外延层。

5. 发明授权

US06222230B1 Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation 有权
标题翻译：用增强的梯度侧壁制造升高的源极/漏极的方法，用于与间隔物形成集成的晶体管缩放
公开(公告)号：US06222230B1
公开(公告)日：2001-04-24
申请号：US09204967
申请日：1998-12-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L29/66621 , H01L21/823418 , H01L21/823468 , H01L21/823487 , H01L29/4232 , H01L29/4238
摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.
摘要翻译：提供集成电路及其制造晶体管的方法。在一个方面，集成电路包括基板和位于基板的多个有源区上的多个晶体管。每个晶体管具有位于衬底中的掺杂区域，位于衬底中的锥形沟槽中的绝缘层，其延伸穿过并将掺杂区域划分为第一源极/漏极区域和第二源极/漏极区域。绝缘层是具有基部的沟道形状，第一向上倾斜的侧壁和第二向上倾斜的侧壁。栅电极位于绝缘层上。通道形栅极电介质层需要较少的水平衬底面积，使给定衬底具有更高的堆积密度。倾斜的侧壁作为间隔件加倍，使工艺简化。

6. 发明授权

US06188106B1 MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties 有权
标题翻译： MOSFET具有高度掺杂的沟道衬垫和掺杂剂密封，以提供增强的器件特性
公开(公告)号：US06188106B1
公开(公告)日：2001-02-13
申请号：US09146410
申请日：1998-09-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2978
CPC分类号： H01L29/51 , H01L21/26533 , H01L29/0649 , H01L29/1079 , H01L29/665 , H01L29/6659
摘要： A fabrication process and integrated circuit are provided in which a transistor having increased resistance to punchthrough and decreased channel capacitance is formed. A liner layer is formed within the active region of a transistor to minimize punchthrough. A barrier layer is then formed between the liner layer and the upper surface of the semiconductor substrate. The barrier layer preferably inhibits migration of the liner ions into the junction and channel regions of the transistors during subsequent processing steps. Such migration could deleteriously affect transistor function by, e.g., increasing the threshold voltage and thus decreasing the drive current. The barrier layer also preferably facilitates formation of shallow junctions. In an embodiment, the liner layer may include p-type ions such as boron and the barrier layer may include nitrogen implanted into the semiconductor substrate. Alternatively, the barrier layer may include nitrogen-incorporated epitaxially grown silicon.
摘要翻译：提供一种制造工艺和集成电路，其中形成具有增加的穿透电阻和降低的沟道电容的晶体管。在晶体管的有源区内形成衬垫层以最小化穿透。然后在衬垫层和半导体衬底的上表面之间形成阻挡层。阻挡层优选地在随后的处理步骤期间抑制衬里离子迁移到晶体管的结和沟道区中。这种迁移可以通过例如增加阈值电压并从而降低驱动电流来有害地影响晶体管功能。阻挡层还优选有利于形成浅结。在一个实施例中，衬垫层可以包括诸如硼的p型离子，并且阻挡层可以包括注入到半导体衬底中的氮。或者，阻挡层可以包括掺入氮的外延生长的硅。

7. 发明授权

US6159804A Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length 失效
标题翻译：制造具有超短沟道长度的晶体管的一次性侧壁氧化制造方法
公开(公告)号：US6159804A
公开(公告)日：2000-12-12
申请号：US145663
申请日：1998-09-02
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/72
CPC分类号： H01L29/66659 , H01L21/28132 , H01L21/823425 , H01L21/823468
摘要： The present invention is directed to a method of making a transistor having a very short channel length. The method generally comprises forming a plurality of process layers above a surface of a semiconducting substrate, one of the process layers being comprised of a gate dielectric material and another of the process layers being comprised of a gate conductor material. The method further comprises patterning the plurality of process layers to define an opening and forming a first sidewall spacer in the opening adjacent at least the process layer comprised of a gate conductor material. The method continues with the formation of a gate conductor mask by oxidation of a portion of at least one of the process layers other than those layers comprised of a gate dielectric material and the gate conductor material. A portion of the process layer comprised of a gate conductor material is then removed to define a gate conductor positioned beneath the gate conductor mask, followed by the formation of a second sidewall spacer adjacent the gate conductor. Thereafter, at least one source/drain region is formed to complete the transistor formation. The present invention further comprises a transistor having a channel length of less than 1000 .ANG..
摘要翻译：本发明涉及一种制造具有非常短的通道长度的晶体管的方法。该方法通常包括在半导体衬底的表面上方形成多个工艺层，其中一个工艺层由栅极电介质材料构成，另一个工艺层由栅极导体材料构成。该方法还包括对多个处理层进行图案化以限定开口，并且在开口中形成邻近至少由栅极导体材料构成的工艺层的第一侧壁间隔物。该方法继续通过除了由栅极电介质材料和栅极导体材料构成的那些层之外的至少一个工艺层的一部分的氧化形成栅极导体掩模。然后移除由栅极导体材料构成的工艺层的一部分，以限定位于栅极导体掩模下方的栅极导体，随后形成邻近栅极导体的第二侧壁间隔物。此后，形成至少一个源极/漏极区以完成晶体管的形成。本发明还包括具有小于1000安培的通道长度的晶体管。

8. 发明授权

US5882983A Trench isolation structure partially bound between a pair of low K dielectric structures 失效
标题翻译：沟槽隔离结构部分地结合在一对低K电介质结构之间
公开(公告)号：US5882983A
公开(公告)日：1999-03-16
申请号：US994143
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/762 , H01L21/326 , H01L21/76
CPC分类号： H01L21/76237
摘要： A process is provided for forming to dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate. The sidewall spacers permit the lateral width of the spacers to be reduced below the minimum lateral dimension definable using lithography. A trench dielectric is formed within the trench such that the upper portion of the dielectric is bound by the sidewall spacers on opposite ends. The resulting trench isolation structure is less likely to experience current leakage when operating an ensuing integrated circuit which employs the isolation structure.
摘要翻译：提供了一种用于形成具有邻近沟槽隔离结构的相对侧边缘布置的相对低的介电常数的电介质结构的工艺。在一个实施例中，通过布置在半导体衬底上的掩模层垂直蚀刻开口，从而暴露衬底的表面。使用光刻法在掩模层上形成图案化的光致抗蚀剂层，以限定待蚀刻的区域。由低K电介质材料制成的侧壁隔离物形成在开口内的掩蔽层的相对的侧壁表面上。通过在开口内CVD沉积电介质材料并各向异性地蚀刻电介质材料形成侧壁间隔物，直到材料的预定厚度仅保留在掩模层侧壁表面上为止。此后，在衬底内形成限定在侧壁间隔物的暴露的横向边缘之间的沟槽。侧壁间隔件允许间隔物的横向宽度减小到使用光刻可定义的最小横向尺寸以下。在沟槽内形成沟槽电介质，使得电介质的上部由相对端上的侧壁间隔件结合。当使用隔离结构的随后集成电路进行操作时，所得到的沟槽隔离结构不太可能经历电流泄漏。

9. 发明授权

US06531364B1 Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer 有权
标题翻译：使用牺牲多晶硅种子层形成超薄栅极电介质的先进制造技术
公开(公告)号：US06531364B1
公开(公告)日：2003-03-11
申请号：US09129703
申请日：1998-08-05
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/518
摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
摘要翻译：提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。然后可以将牺牲多晶硅层还原成所需的厚度。牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。作为选择，可以加热牺牲多晶硅层使其重结晶。牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。

10. 发明授权

US06303962B1 Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures 有权
标题翻译：具有低电阻金属源和漏极的绝缘隔离晶体管，使用牺牲源极和漏极结构形成
公开(公告)号：US06303962B1
公开(公告)日：2001-10-16
申请号：US09227512
申请日：1999-01-06
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： A01L2701
CPC分类号： H01L29/66757 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/78675
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。晶体管的栅极也可以由诸如金属的低电阻材料形成。晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。

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