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1. 发明授权

US07046174B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US07046174B1
公开(公告)日：2006-05-16
申请号：US11147757
申请日：2005-06-07
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0331
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

2. 发明授权

US06724328B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06724328B1
公开(公告)日：2004-04-20
申请号：US10454626
申请日：2003-06-03
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M900
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

3. 发明授权

US06970117B1 Byte alignment for serial data receiver 失效
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06970117B1
公开(公告)日：2005-11-29
申请号：US10789406
申请日：2004-02-26
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00 , H04L7/02
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

4. 发明授权

US06867616B1 Programmable logic device serial interface having dual-use phase-locked loop circuitry 有权
标题翻译：具有双用途锁相环电路的可编程逻辑器件串行接口
公开(公告)号：US06867616B1
公开(公告)日：2005-03-15
申请号：US10455773
申请日：2003-06-04
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H03K19/173 , H03D3/24
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.
摘要翻译：在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

5. 发明授权

US07071726B1 Selectable dynamic reconfiguration of programmable embedded IP 失效
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US07071726B1
公开(公告)日：2006-07-04
申请号：US11005390
申请日：2004-12-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

6. 发明授权

US07151470B1 Data converter with multiple conversions for padded-protocol interface 有权
标题翻译：具有多个转换的数据转换器，用于填充协议接口
公开(公告)号：US07151470B1
公开(公告)日：2006-12-19
申请号：US10969450
申请日：2004-10-20
申请人： Ning Xue , Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ning Xue , Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： H03M7/00
CPC分类号： H03M7/04
摘要： A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.
摘要翻译：用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换，例如在64位和66位之间，在24位和26位之间，或在48位和50位之间。这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的，这些时钟速度全部来自相同的主时钟（可以从接收机实施例中的数据恢复）。当转换不是设计齿轮箱的最大宽度的转换时，未使用的位将被忽略。转换器还可以在不同宽度的数据中找到用于对齐目的的填充位，当数据不是设计转换器的最宽时，再次忽略未使用的位。

7. 发明授权

US06888376B1 Multiple data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US06888376B1
公开(公告)日：2005-05-03
申请号：US10670845
申请日：2003-09-24
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/1778 , H03K19/17796
摘要： A serial interface for a programmable logic device supports a higher physical medium attachment (“PMA”) data rate than the available physical coding sublayer (“PCS”) data rate by using multiple PCS modules, operating in parallel, to support one PMA module. In a channel-based structure, the PMA module is supported by a PCS module in its own channel and at least one PCS module from a second channel. The second channel may include its own PMA module which, if provided, may operate at a lower rate, supportable by the PCS module in that channel. Optionally, two modes are provided. In one mode, two PCS modules in two channels support one higher-speed PMA module in one of the channels. In a second mode, each PCS module supports a PMA module in its own channel, with the higher-speed PMA module constrained to operate at the lower data rate of the PCS module.
摘要翻译：用于可编程逻辑器件的串行接口通过使用并行操作的多个PCS模块来支持比可用物理编码子层（“PCS”）数据速率更高的物理介质附加（“PMA”）数据速率，以支持一个PMA模块。在基于通道的结构中，PMA模块由其自身通道中的PCS模块和来自第二通道的至少一个PCS模块支持。第二通道可以包括其自己的PMA模块，如果提供的话，该模块可以以较低的速率操作，由PCS模块在该通道中支持。可选地，提供两种模式。在一种模式下，两个通道中的两个PCS模块在其中一个通道中支持一个更高速的PMA模块。在第二种模式下，每个PCS模块都支持自己的通道中的PMA模块，而高速PMA模块则被限制在PCS模块的较低数据速率下工作。

8. 发明授权

US06963223B2 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
公开(公告)号：US06963223B2
公开(公告)日：2005-11-08
申请号：US10835081
申请日：2004-04-28
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H04Q11/04
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

9. 发明授权

US06750675B2 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
标题翻译：可编程逻辑器件具有多标准字节同步和通道对齐通讯
公开(公告)号：US06750675B2
公开(公告)日：2004-06-15
申请号：US10195229
申请日：2002-07-11
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： A03K19177
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
摘要翻译：可编程逻辑器件（“PLD”）包括通信接口电路，其可以支持任何广泛的通信协议，包括分组超声波（“POS-5”）和8位/ 10比特（“8B10B”）协议。接口电路包括至少部分硬连线以执行特定类型的功能的各种功能块，但是在至少许多情况下也可部分地可编程以允许基本功能适应各种协议。对各种功能块之间，之间和/或周围的信号的路由也优选地至少可部分地可编程以便于以各种方式组合功能块来支持各种协议。

10. 发明授权

US07362833B1 Dynamic special character selection for use in byte alignment circuitry 有权
标题翻译：用于字节对齐电路的动态特殊字符选择
公开(公告)号：US07362833B1
公开(公告)日：2008-04-22
申请号：US10609091
申请日：2003-06-27
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
IPC分类号： H04B1/10
CPC分类号： H04J3/0608
摘要： Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When circuitry detects this information, it can align the byte boundaries and thereby provide byte-aligned data to utilization circuitry (e.g., a programmable logic device). In accordance with this invention, circuitry can select different special characters for use in detecting the byte boundaries, where the special characters are different lengths. Circuitry aligns the byte boundaries based on the selected special character when enabled by a control signal. Once aligned, circuitry can provide a signal indicating which special character was used to align the boundaries. Another advantage of the invention is that it eliminates alignment problems associated with system latency. Circuitry automatically locks alignment to a first instance of a detected special character independent of an external control signal.
摘要翻译：提供了用于定位数据流中字节边界的电路。数据流通常具有提供字节边界指示的逗号或头信息。当电路检测到该信息时，它可以对齐字节边界，从而向利用电路（例如，可编程逻辑器件）提供字节对齐的数据。根据本发明，电路可以选择用于检测字节边界的不同特殊字符，其中特殊字符是不同的长度。当控制信号使能时，电路会根据所选择的特殊字符对齐字节边界。一旦对准，电路可以提供一个信号，指示哪个特殊字符用于对齐边界。本发明的另一个优点是它消除了与系统延迟相关联的对准问题。电路自动将校准锁定到独立于外部控制信号的检测到的特殊字符的第一实例。

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