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1. 发明授权

US09515880B1 Integrated circuits with clock selection circuitry 有权
标题翻译：具有时钟选择电路的集成电路
公开(公告)号：US09515880B1
公开(公告)日：2016-12-06
申请号：US13338898
申请日：2011-12-28
申请人： Ramanand Venkata , Henry Y. Lui , Victor Maruri , David W. Mendel , Andrew Bellis
发明人： Ramanand Venkata , Henry Y. Lui , Victor Maruri , David W. Mendel , Andrew Bellis
IPC分类号： G06F15/177 , G06F1/00 , G06F1/04 , G06F15/16 , H04L12/24 , G06F1/10 , G06F17/50 , G06F9/445
CPC分类号： H04L41/0816 , G06F1/04 , G06F1/10 , G06F9/44505 , G06F17/5054 , H04J3/0688 , H04J3/0691 , H04J3/0697 , H04L41/0813
摘要： An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.
摘要翻译：集成电路设备可以包括可以动态地重新配置以执行不同的任务的处理电路，每个任务利用不同的系统时钟资源。该装置可以包括时钟选择电路，其可以选择性地将期望的时钟信号路由到相应的处理电路。可以基于该处理电路的当前配置来选择提供给每个处理电路的时钟信号。网络交换机中的客户端处理电路可以耦合到可互换的客户端网络。可以基于当前耦合到网络交换机的客户端网络的特性来动态地重新配置客户端处理电路。通过动态地选择哪些时钟资源被提供给处理电路，诸如相对稀少的全局时钟信号的时钟资源可以被保留用于只能用相对稀少的时钟资源起作用的处理电路。以这种方式安排，可以不断优化时钟资源利用。

2. 发明授权

US07659838B2 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
公开(公告)号：US07659838B2
公开(公告)日：2010-02-09
申请号：US11359273
申请日：2006-02-21
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。电路也可以在宽频率范围内的任何频率下工作。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

3. 发明申请

US20070011370A1 Multiple data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US20070011370A1
公开(公告)日：2007-01-11
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： G06F13/38
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

4. 发明授权

US07039787B1 Byte alignment circuitry 失效
标题翻译：字节对齐电路
公开(公告)号：US07039787B1
公开(公告)日：2006-05-02
申请号：US10984684
申请日：2004-11-09
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/4018 , H04J3/0608
摘要： Circuitry for locating the boundaries between bytes in a data stream is only selectively enabled to find a possible new byte alignment by a control signal. After the byte alignment circuitry has found a byte alignment, it outputs byte-aligned data and a first status signal indicating the presence of such data. If the byte alignment circuitry subsequently detects information that suggests a possible need for a new or changed byte alignment, it outputs a second status signal to that effect. However, the byte alignment circuitry does not actually attempt to change its byte alignment until enabled to do so by the control signal. Programmable logic circuitry or other utilization circuitry is typically provided to receive the outputs of the byte alignment circuitry and to selectively provide the control signal.
摘要翻译：用于定位数据流中的字节之间的边界的电路仅被选择性地用于通过控制信号找到可能的新字节对齐。在字节对齐电路找到一个字节对齐之后，它输出字节对齐的数据和指示这种数据的存在的第一状态信号。如果字节对齐电路随后检测到提示可能需要新的或改变的字节对齐的信息，则输出第二状态信号。然而，字节对齐电路实际上并不会尝试改变其字节对齐，直到通过控制信号使其能够这样做。通常提供可编程逻辑电路或其他利用电路以接收字节对准电路的输出并选择性地提供控制信号。

5. 发明申请

US20060012394A1 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
公开(公告)号：US20060012394A1
公开(公告)日：2006-01-19
申请号：US11189209
申请日：2005-07-26
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

6. 发明授权

US06867616B1 Programmable logic device serial interface having dual-use phase-locked loop circuitry 有权
标题翻译：具有双用途锁相环电路的可编程逻辑器件串行接口
公开(公告)号：US06867616B1
公开(公告)日：2005-03-15
申请号：US10455773
申请日：2003-06-04
申请人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H. Lee , Rakesh Patel
IPC分类号： H03K19/177 , H03K19/173 , H03D3/24
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.
摘要翻译：在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

7. 发明授权

US08923440B1 Circuitry for padded communication protocols 有权
标题翻译：用于填充通信协议的电路
公开(公告)号：US08923440B1
公开(公告)日：2014-12-30
申请号：US12284191
申请日：2008-09-19
申请人： Ramanand Venkata , Binh Ton
发明人： Ramanand Venkata , Binh Ton
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L25/4908 , H04J3/0605 , H04J3/062 , H04J3/0685 , H04J3/07 , H04L1/0064
摘要： Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.
摘要翻译：用于64b / 66b编码或其他类似填充数据信令的发射机和接收机电路。通过使用一个时钟信号源作为在填充之前和之后至少部分地处理数据的基础来简化所需的发送器时钟电路。采用适当的倍频和除数因子使其成为可能。在接收机电路中使用类似的技术。

8. 发明授权

US08581653B1 Techniques for providing clock signals in clock networks 有权
标题翻译：在时钟网络中提供时钟信号的技术
公开(公告)号：US08581653B1
公开(公告)日：2013-11-12
申请号：US13328784
申请日：2011-12-16
申请人： Victor Maruri , Arch Zaliznyak , Ramanand Venkata , Henry Y. Lui
发明人： Victor Maruri , Arch Zaliznyak , Ramanand Venkata , Henry Y. Lui
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.
摘要翻译：集成电路包括可操作以提供第一时钟信号的本地时钟网络和耦合以从本地时钟网络接收第一时钟信号的接口电路。接口电路可操作以基于第一时钟信号产生第二时钟信号。时钟线耦合到接口电路。时钟线具有固定长度。第二时钟信号通过时钟线提供给多路复用器电路。多路复用器电路基于第二时钟信号提供第三时钟信号。另一个时钟网络被耦合以从多路复用器电路接收第三时钟信号。

9. 发明申请

US20110090101A1 DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS 有权
标题翻译：数字相位锁定环路和方法
公开(公告)号：US20110090101A1
公开(公告)日：2011-04-21
申请号：US12974949
申请日：2010-12-21
申请人： Ramanand Venkata , Chong H. Lee
发明人： Ramanand Venkata , Chong H. Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03L7/089 , H03L2207/50 , H04L7/0008 , H04L7/0337
摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
摘要翻译：锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换。该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。出于同样的原因，发射侧可能会使用过量传输或过采样。

10. 发明授权

US07698482B2 Multiple data rates in integrated circuit device serial interface 有权
标题翻译：集成电路设备串行接口中的多种数据速率
公开(公告)号：US07698482B2
公开(公告)日：2010-04-13
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
发明人： Ramanand Venkata , Rakesh H. Patel , Chong H. Lee
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

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