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1. 发明授权

US07071726B1 Selectable dynamic reconfiguration of programmable embedded IP 失效
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US07071726B1
公开(公告)日：2006-07-04
申请号：US11005390
申请日：2004-12-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

2. 发明授权

US07362833B1 Dynamic special character selection for use in byte alignment circuitry 有权
标题翻译：用于字节对齐电路的动态特殊字符选择
公开(公告)号：US07362833B1
公开(公告)日：2008-04-22
申请号：US10609091
申请日：2003-06-27
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
IPC分类号： H04B1/10
CPC分类号： H04J3/0608
摘要： Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When circuitry detects this information, it can align the byte boundaries and thereby provide byte-aligned data to utilization circuitry (e.g., a programmable logic device). In accordance with this invention, circuitry can select different special characters for use in detecting the byte boundaries, where the special characters are different lengths. Circuitry aligns the byte boundaries based on the selected special character when enabled by a control signal. Once aligned, circuitry can provide a signal indicating which special character was used to align the boundaries. Another advantage of the invention is that it eliminates alignment problems associated with system latency. Circuitry automatically locks alignment to a first instance of a detected special character independent of an external control signal.
摘要翻译：提供了用于定位数据流中字节边界的电路。数据流通常具有提供字节边界指示的逗号或头信息。当电路检测到该信息时，它可以对齐字节边界，从而向利用电路（例如，可编程逻辑器件）提供字节对齐的数据。根据本发明，电路可以选择用于检测字节边界的不同特殊字符，其中特殊字符是不同的长度。当控制信号使能时，电路会根据所选择的特殊字符对齐字节边界。一旦对准，电路可以提供一个信号，指示哪个特殊字符用于对齐边界。本发明的另一个优点是它消除了与系统延迟相关联的对准问题。电路自动将校准锁定到独立于外部控制信号的检测到的特殊字符的第一实例。

3. 发明授权

US06842034B1 Selectable dynamic reconfiguration of programmable embedded IP 有权
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US06842034B1
公开(公告)日：2005-01-11
申请号：US10612253
申请日：2003-07-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

4. 发明授权

US07046174B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US07046174B1
公开(公告)日：2006-05-16
申请号：US11147757
申请日：2005-06-07
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0331
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

5. 发明授权

US06724328B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06724328B1
公开(公告)日：2004-04-20
申请号：US10454626
申请日：2003-06-03
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M900
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

6. 发明授权

US06970117B1 Byte alignment for serial data receiver 失效
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06970117B1
公开(公告)日：2005-11-29
申请号：US10789406
申请日：2004-02-26
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00 , H04L7/02
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

7. 发明申请

US20070011370A1 Multiple data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US20070011370A1
公开(公告)日：2007-01-11
申请号：US11177007
申请日：2005-07-08
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： G06F13/38
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
摘要翻译：用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道界面最好是四。每个通道优选地包括物理介质连接模块和物理编码子层模块。第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

8. 发明申请

US20060012394A1 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
公开(公告)号：US20060012394A1
公开(公告)日：2006-01-19
申请号：US11189209
申请日：2005-07-26
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

9. 发明申请

US20070188189A1 PROGRAMMABLE LOGIC DEVICE WITH SERIAL INTERCONNECT 有权
标题翻译：具有串行互连的可编程逻辑器件
公开(公告)号：US20070188189A1
公开(公告)日：2007-08-16
申请号：US11539006
申请日：2006-10-05
申请人： Ramanand Venkata , Rakesh Patel , Chong Lee
发明人： Ramanand Venkata , Rakesh Patel , Chong Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17784
摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.
摘要翻译：在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。设备上的部分或全部功能块被补充有串行接口。尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。这意味着设备功耗的显着降低。串行接口可以与全局设备时钟（例如PLL）同步工作。在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口块将不得不更复杂，因为它们必须能够与外部设备异步操作。

10. 发明申请

US20060233172A1 Multiple data rates in programmable logic device serial interface 失效
公开(公告)号：US20060233172A1
公开(公告)日：2006-10-19
申请号：US11177034
申请日：2005-07-08
申请人： Ramanand Venkata , Chong Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong Lee , Rakesh Patel
IPC分类号： H04L12/28
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

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