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1. 发明授权

US07151470B1 Data converter with multiple conversions for padded-protocol interface 有权
标题翻译：具有多个转换的数据转换器，用于填充协议接口
公开(公告)号：US07151470B1
公开(公告)日：2006-12-19
申请号：US10969450
申请日：2004-10-20
申请人： Ning Xue , Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ning Xue , Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： H03M7/00
CPC分类号： H03M7/04
摘要： A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.
摘要翻译：用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换，例如在64位和66位之间，在24位和26位之间，或在48位和50位之间。这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的，这些时钟速度全部来自相同的主时钟（可以从接收机实施例中的数据恢复）。当转换不是设计齿轮箱的最大宽度的转换时，未使用的位将被忽略。转换器还可以在不同宽度的数据中找到用于对齐目的的填充位，当数据不是设计转换器的最宽时，再次忽略未使用的位。

2. 发明授权

US07577166B2 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication 有权
标题翻译：可编程逻辑器件具有多标准字节同步和通道对齐通讯
公开(公告)号：US07577166B2
公开(公告)日：2009-08-18
申请号：US11189209
申请日：2005-07-26
申请人： Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： H04J3/07
CPC分类号： H03K19/17744 , H03K19/17732 , H04J3/1617 , H04J2203/0082 , H04J2203/0094
摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
摘要翻译：可编程逻辑器件（“PLD”）包括通信接口电路，其可以支持任何广泛的通信协议，包括分组超声波（“POS-5”）和8位/ 10比特（“8B10B”）协议。接口电路包括至少部分硬连线以执行特定类型的功能的各种功能块，但是在至少许多情况下也可部分地可编程以允许基本功能适应各种协议。对各种功能块之间，之间和/或周围的信号的路由也优选地至少可部分地可编程以便于以各种方式组合功能块来支持各种协议。

3. 发明授权

US07272677B1 Multi-channel synchronization for programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口的多通道同步
公开(公告)号：US07272677B1
公开(公告)日：2007-09-18
申请号：US10637982
申请日：2003-08-08
申请人： Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： H03K19/1774 , G06F1/12 , H03K19/17744 , H03K19/17792
摘要： A serial interface for a programmable logic device substantially eliminates skew across multiple channels both in the receiver and in the transmitter. Even when the channels are independent (e.g., are in different quads), skew is substantially eliminated by monitoring to determine when all channels have reached their active states (i.e., in the case of receiver channels when all channels have achieved byte alignment and have received an alignment character, and in the case of transmitter channels when all transmit PLLs have locked), and only then allowing data to flow between the serial and parallel domains.
摘要翻译：用于可编程逻辑器件的串行接口基本上消除了接收器和发射器中的多个通道的偏移。即使当信道是独立的（例如，处于不同的四边形）时，通过监视基本上消除了偏差，以便确定所有信道何时已经达到其活动状态（即，在所有信道已经实现字节对齐并已经接收到的信道的情况下对齐字符，并且在所有发送PLL锁定时在发送器通道的情况下），并且仅允许数据在串行和并行域之间流动。

4. 发明授权

US07131024B1 Multiple transmit data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个传输数据速率
公开(公告)号：US07131024B1
公开(公告)日：2006-10-31
申请号：US10670813
申请日：2003-09-24
申请人： Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： G06F1/06
CPC分类号： G06F1/06
摘要： A serial interface for a programmable logic device provides multiple data rates in different channels by generating a central serial clock and providing at least one divider in each channel that can divide the central clock by different integer values. For additional variation in clock rate, two or more different central clocks can be provided, with each channel then being able to divide any of the central clocks to provide the desired local clock. Lower speed parallel clocks can be generated locally by further dividing the divided serial clock. Alternatively, the central serial clock or clocks may be divided centrally to provide a central parallel clock or clocks which can then be used locally as a local parallel clock.
摘要翻译：用于可编程逻辑器件的串行接口通过产生中央串行时钟来在不同的通道中提供多个数据速率，并且在每个通道中提供至少一个可以将中心时钟除以不同整数值的分频器。对于时钟速率的额外变化，可以提供两个或多个不同的中央时钟，每个信道然后能够分割任何中央时钟以提供期望的本地时钟。可以通过进一步分割串行时钟来本地生成低速并行时钟。或者，中央串行时钟可以集中分配以提供中央并行时钟或时钟，然后可以将其本地地用作本地并行时钟。

5. 发明授权

US07436210B2 Next generation 8B10B architecture 有权
标题翻译：下一代8B10B架构
公开(公告)号：US07436210B2
公开(公告)日：2008-10-14
申请号：US11655797
申请日：2007-01-18
申请人： Ramanand Venkata , Rakesh H Patel , Chong H Lee
发明人： Ramanand Venkata , Rakesh H Patel , Chong H Lee
IPC分类号： H03K19/173
CPC分类号： G06F13/385
摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.
摘要翻译：在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

6. 发明授权

US07869553B1 Digital phase locked loop circuitry and methods 有权
标题翻译：数字锁相环电路及方法
公开(公告)号：US07869553B1
公开(公告)日：2011-01-11
申请号：US10923129
申请日：2004-08-20
申请人： Ramanand Venkata , Chong H Lee
发明人： Ramanand Venkata , Chong H Lee
IPC分类号： H03D3/24
CPC分类号： H03M9/00 , H03L7/089 , H03L2207/50 , H04L7/0008 , H04L7/0337
摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
摘要翻译：锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换。该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。出于同样的原因，发射侧可能会使用过量传输或过采样。

7. 发明授权

US07305058B1 Multi-standard clock rate matching circuitry 有权
标题翻译：多标准时钟速率匹配电路
公开(公告)号：US07305058B1
公开(公告)日：2007-12-04
申请号：US10317264
申请日：2002-12-10
申请人： Ramanand Venkata , Chong H Lee
发明人： Ramanand Venkata , Chong H Lee
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H04J3/0632 , H04L7/005
摘要： Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication protocols, the clock rate matching circuitry includes dedicated control circuitry and is also associated with other circuitry that is capable of acting as control circuitry that can be used as an alternative to at least part of the dedicated control circuitry. For example, the dedicated control circuitry may be set up to support one or several industry-standard protocols. The other circuitry (which may be, for example, programmable logic circuitry) is available to support any of a wide range of other protocols, whether industry-standard or custom.
摘要翻译：提供时钟速率匹配电路以缓冲可能具有稍微不同频率的两个时钟域之间的数据。为了便于支持各种不同的通信协议，时钟速率匹配电路包括专用控制电路，并且还与能够充当控制电路的其他电路相关联，该电路可用作至少部分专用控制的替代电路。例如，专用控制电路可以被设置为支持一个或多个行业标准协议。其他电路（可能是例如可编程逻辑电路）可用于支持任何其他协议，无论是工业标准还是定制。

8. 发明授权

US07183797B2 Next generation 8B10B architecture 有权
标题翻译：下一代8B10B架构
公开(公告)号：US07183797B2
公开(公告)日：2007-02-27
申请号：US10977952
申请日：2004-10-29
申请人： Ramanand Venkata , Rakesh H Patel , Chong H Lee
发明人： Ramanand Venkata , Rakesh H Patel , Chong H Lee
IPC分类号： H03K19/173
CPC分类号： G06F13/385
摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.
摘要翻译：在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

9. 发明授权

US07538578B2 Multiple data rates in programmable logic device serial interface 失效
标题翻译：可编程逻辑器件串行接口中的多个数据速率
公开(公告)号：US07538578B2
公开(公告)日：2009-05-26
申请号：US11177034
申请日：2005-07-08
申请人： Ramanand Venkata , Chong H Lee , Rakesh H Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh H Patel
IPC分类号： H03K19/177 , G06F13/42
CPC分类号： H03K19/17744
摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.
摘要翻译：用于可编程逻辑器件的串行接口可以根据各种通信协议进行操作，并且包括接收器部分和发射器部分。接收器部分至少包括字或字节对准级，去偏移级，速率补偿或匹配级，填充协议解码器级（例如，8B / 10B解码器电路或64B / 66B解码器电路），字节解串器阶段，字节重排阶段和相位补偿阶段。发射机部分至少包括相位补偿级，字节解串器级和填充协议编码器级（例如，8B / 10B编码器电路或64B / 66B编码器电路）。每个阶段可能有多次出现相关的电路。选择电路，例如多路复用器，为所使用的协议选择适当的阶段和每个阶段内的电路。

10. 发明授权

US07180972B1 Clock signal circuitry for multi-protocol high-speed serial interface circuitry 有权
标题翻译：用于多协议高速串行接口电路的时钟信号电路
公开(公告)号：US07180972B1
公开(公告)日：2007-02-20
申请号：US10273899
申请日：2002-10-16
申请人： Ramanand Venkata , Chong H Lee
发明人： Ramanand Venkata , Chong H Lee
IPC分类号： H04L7/00
CPC分类号： G06F1/10
摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.
摘要翻译：可编程逻辑器件（“PLD”）包括高速串行接口（“HSSI”）电路。 HSSI电路包括时钟信号电路，其允许HSSI电路的各种组件以不同的方式计时，以便于使用HSSI电路来支持多种不同的通信协议。一些HSSI时钟信号可以通过相关联的PLD逻辑电路的时钟分配网络路由。 HSSI电路可以包括相位补偿缓冲器电路，以补偿跨越HSSI电路和相关联的PLD逻辑电路之间的接口上的可能的相位差。

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