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1. 发明授权

US06838332B1 Method for forming a semiconductor device having electrical contact from opposite sides 有权
标题翻译：用于形成具有来自相对侧的电接触的半导体器件的方法
公开(公告)号：US06838332B1
公开(公告)日：2005-01-04
申请号：US10641544
申请日：2003-08-15
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L21/8242 , H01L21/20 , H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

2. 发明授权

US06921961B2 Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region 有权
标题翻译：具有从相对侧电接触的半导体器件，包括形成在扩散区域的底表面处的端部的通孔
公开(公告)号：US06921961B2
公开(公告)日：2005-07-26
申请号：US10946758
申请日：2004-09-22
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L29/00 , H01L29/06 , H01L29/40
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连件（68）连接的直接下伏的无源器件（例如电容器）（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

3. 发明授权

US07122421B2 Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element 有权
标题翻译：包括具有对准的晶体管和电容元件的晶体管和电容器的半导体器件
公开(公告)号：US07122421B2
公开(公告)日：2006-10-17
申请号：US11098070
申请日：2005-04-04
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

4. 发明授权

US07176574B2 Semiconductor device having a multiple thickness interconnect 有权
标题翻译：具有多重厚度互连的半导体器件
公开(公告)号：US07176574B2
公开(公告)日：2007-02-13
申请号：US10946675
申请日：2004-09-22
申请人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
发明人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
摘要翻译：导线的厚度变化，有助于克服RC延迟和噪声耦合。通过改变线路厚度，如果需要在导体之间保持规定的最小间距，同时保持预定的期望的RC参数和导线的噪声特性，则避免导体宽度的变化。通过将介电层蚀刻成不同的厚度来实现导体深度变化。电介质层上的不同厚度的导电填充导致厚度变化的导线。在特定金属水平可用的不同的导线厚度可以另外用于除信号或电源导线之外的半导体结构，例如器件的触点，通孔或电极。为了满足期望的设计标准，确定互连厚度如何变化所需的厚度分析可以是自动化的并且作为CAD工具提供。

5. 发明授权

US06815820B2 Method for forming a semiconductor interconnect with multiple thickness 有权
标题翻译：用于形成具有多个厚度的半导体互连的方法
公开(公告)号：US06815820B2
公开(公告)日：2004-11-09
申请号：US10141714
申请日：2002-05-09
申请人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
发明人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

6. 发明授权

US07030001B2 Method for forming a gate electrode having a metal 失效
标题翻译：用于形成具有金属的栅电极的方法
公开(公告)号：US07030001B2
公开(公告)日：2006-04-18
申请号：US10827202
申请日：2004-04-19
申请人： Olubunmi O. Adetutu , Lynne M. Michaelson , Kathleen C. Yu , Robert E. Jones, Jr.
发明人： Olubunmi O. Adetutu , Lynne M. Michaelson , Kathleen C. Yu , Robert E. Jones, Jr.
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , B82Y10/00 , B82Y30/00 , C23C16/042 , H01L21/28079 , H01L29/495 , H01L29/4958 , H01L29/7833
摘要： One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
摘要翻译：一个实施例在衬底上形成栅极电介质层，然后在其中将形成第一器件类型的栅极电介质层的部分上选择性地沉积第一金属层。不同于第一金属层的第二金属层形成在将形成第二器件类型的栅极电介质层的暴露部分上。第一和第二装置类型中的每一种将具有不同的功函数，因为每个将包括与栅极电介质直接接触的不同金属。在一个实施例中，第一金属层的选择性沉积由ALD执行，并且使用抑制层，其选择性地形成在栅极电介质层上，使得第一金属层可以仅选择性地沉积在栅极的那些部分未被抑制层覆盖的介电层。

7. 发明授权

US07904869B2 Method of area compaction for integrated circuit layout design 有权
标题翻译：集成电路布局设计的面积压实方法
公开(公告)号：US07904869B2
公开(公告)日：2011-03-08
申请号：US11958605
申请日：2007-12-18
申请人： Kathleen C. Yu , Scott D. Hector , Robert L. Maziasz , Claudia A. Stanley , James E. Vasck
发明人： Kathleen C. Yu , Scott D. Hector , Robert L. Maziasz , Claudia A. Stanley , James E. Vasck
IPC分类号： G06F9/455
CPC分类号： G06F17/5068 , G06F17/5081
摘要： A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
摘要翻译：集成电路布局设计的面积压缩方法包括确定至少第一电路和第二电路构建块的每层的物理范围边界。确定物理范围边界包括确定第一电路的每个相应层和第二电路构建块（i）使用部分和（ii）自由部分。所使用的部分对应于各个电路构建块的功能部分，并且自由部分对应于各个电路构建块的非功能部分。该方法还包括分别相对于第一电路和第二电路构建块的每层的确定的物理范围边界建立包装密钥。包装键限定了相应的第一电路或第二电路构建块与另一个电路构建块的压实的互锁特性。

8. 发明授权

US06838354B2 Method for forming a passivation layer for air gap formation 有权
标题翻译：形成气隙形成钝化层的方法
公开(公告)号：US06838354B2
公开(公告)日：2005-01-04
申请号：US10327403
申请日：2002-12-20
申请人： Cindy K. Goldberg , Stanley Michael Filipiak , John C. Flake , Yeong-Jyh T. Lii , Bradley P. Smith , Yuri E. Solomentsev , Terry G. Sparks , Kirk J. Strozewski , Kathleen C. Yu
发明人： Cindy K. Goldberg , Stanley Michael Filipiak , John C. Flake , Yeong-Jyh T. Lii , Bradley P. Smith , Yuri E. Solomentsev , Terry G. Sparks , Kirk J. Strozewski , Kathleen C. Yu
IPC分类号： H01L21/288 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76844 , H01L21/288 , H01L21/7682 , H01L21/76849 , H01L21/76874
摘要： Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

9. 发明授权

US06764919B2 Method for providing a dummy feature and structure thereof 有权
标题翻译：提供虚拟特征及其结构的方法
公开(公告)号：US06764919B2
公开(公告)日：2004-07-20
申请号：US10327498
申请日：2002-12-20
申请人： Kathleen C. Yu , Edward O. Travis , Bradley P. Smith
发明人： Kathleen C. Yu , Edward O. Travis , Bradley P. Smith
IPC分类号： H01L2176
CPC分类号： H01L21/76852 , H01L21/7682 , H01L21/76874 , H01L23/522 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.
摘要翻译：在层间电介质层（36）内形成虚拟特征（64,65a，65b，48a，48b）。在虚拟特征（64,65a，65b，48a，48b）上形成无间隙填充介电层（72），以在虚拟特征（64,65a，65b，48a，48b）之间或之间形成空隙（74）虚拟特征（48a）和载流区（44）。虚拟特征（64,65a，65b，48a，48b）可以是导电的（48a，48b），因此在形成载流区域（44）时形成。在另一个实施例中，虚拟特征（64,65a，65b，48a，48b）是绝缘的（64,65a，65b），并且在形成载流区域（44）之后形成。在又一个实施例中，形成导电和绝缘虚拟特征（64,65a，65b，48a，48b）。在优选实施例中，空隙（74）是作为低介电常数材料的气隙。

10. 发明申请

US20090158229A1 METHOD OF AREA COMPACTION FOR INTEGRATED CIRCUIT LAYOUT DESIGN 有权
标题翻译：集成电路布局设计领域融合方法
公开(公告)号：US20090158229A1
公开(公告)日：2009-06-18
申请号：US11958605
申请日：2007-12-18
申请人： Kathleen C. Yu , Scott D. Hector , Robert L. Maziasz , Claudia A. Stanley , James E. Vasck
发明人： Kathleen C. Yu , Scott D. Hector , Robert L. Maziasz , Claudia A. Stanley , James E. Vasck
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
摘要翻译：集成电路布局设计的面积压缩方法包括确定至少第一电路和第二电路构建块的每层的物理范围边界。确定物理范围边界包括确定第一电路的每个相应层和第二电路构建块（i）使用部分和（ii）自由部分。所使用的部分对应于各个电路构建块的功能部分，并且自由部分对应于各个电路构建块的非功能部分。该方法还包括分别相对于第一电路和第二电路构建块的每层的确定的物理范围边界建立包装密钥。包装键限定了相应的第一电路或第二电路构建块与另一个电路构建块的压实的互锁特性。

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