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1. 发明专利

JP2006310718A Transistor structure of memory device and its manufacturing method 审中-公开
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：JP2006310718A
公开(公告)日：2006-11-09
申请号：JP2005188007
申请日：2005-06-28
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： JANG SE AUG , KIM YONG-SOO , OH JAE-GEUN , RO SAISEI , SOHN HYUN-CHUL
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： PROBLEM TO BE SOLVED: To provide a transistor structure of a memory device in a new form, and to provide the manufacturing method of the transistor structure.
SOLUTION: The transistor is provided with an active region 111a projected from a prescribe region of a substrate 111, a recessed groove (g) formed in a channel region in the active region, a field oxide film 112 which is formed on the substrate around the active region and has a surface positioned lower than the upper face of the active region comprising the recessed groove, gate insulating films 113 formed in the recessed groove and on the active region whose surface is exposed and a gate electrode 114 which is overlapped with the recessed groove, crosses on the active region, and extends. An X-X' cross-section along source and drain lines is a recess transistor structure, and a Y-Y' cross-section along a gate line is a projected transistor structure.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供新形式的存储器件的晶体管结构，并提供晶体管结构的制造方法。晶体管设置有从基板111的规定区域突出的有源区域111a，形成在有源区域的沟道区域中的凹槽（g），形成在有源区域中的场氧化物膜112 衬底围绕有源区并且具有位于比包括凹槽的有源区的上表面更低的表面，形成在凹槽中的栅极绝缘膜113和其表面被暴露的有源区和重叠的栅电极114 具有凹槽，在有源区上交叉并延伸。沿着源极和漏极线的X-X'横截面是凹陷晶体管结构，并且沿着栅极线的Y-Y'截面是投射的晶体管结构。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007173789A Method of manufacturing fin transistor 有权
标题翻译：制造FIN晶体管的方法
公开(公告)号：JP2007173789A
公开(公告)日：2007-07-05
申请号：JP2006314879
申请日：2006-11-21
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： SHEEN DONG SUN , SONG SEOK PYO , AHN SANG TAE , SOHN HYUN-CHUL
IPC分类号： H01L21/336 , H01L21/76 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823437 , H01L29/66795 , H01L29/7851
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a fin transistor capable of preventing undesired etching of an SOG layer.
SOLUTION: A method of manufacturing a fin transistor includes: forming a hard mask layer to expose a field region on a silicon substrate having an active region and a field region; forming a trench by etching the exposed substrate field region; filling the trench with an SOG layer, exposing a substrate active region by removing the hard mask layer; forming an epi-silicon layer on the exposed substrate active region; etching the SOG layer so as to fill only a lower layer portion in the trench; depositing an HDP oxide layer on the etched SOG layer so as to fill the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide layer; etching the HDP oxide layer in the field oxide layer so as to expose both side surfaces of the epi-silicon layer; and forming a gate on the epi-silicon layer and the field oxide layer whose both side surfaces are exposed.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造能够防止SOG层的不希望的蚀刻的鳍式晶体管的方法。解决方案：制造鳍式晶体管的方法包括：形成硬掩模层以暴露具有有源区和场区的硅衬底上的场区; 通过蚀刻暴露的衬底区域形成沟槽; 用SOG层填充沟槽，通过去除硬掩模层暴露衬底有源区; 在暴露的衬底有源区上形成外延硅层; 蚀刻SOG层以仅填充沟槽中的下层部分; 在蚀刻的SOG层上沉积HDP氧化物层以填充沟槽，从而形成由SOG层和HDP氧化物层组成的场氧化物层; 蚀刻场氧化物层中的HDP氧化物层，以露出外延硅层的两个侧表面; 以及在其外表面露出的外延硅层和场氧化物层上形成栅极。版权所有（C）2007，JPO＆INPIT

3. 发明专利

DE102004063025B4 Speicherbauelement und Verfahren zur Herstellung desselben 未知
公开(公告)号：DE102004063025B4
公开(公告)日：2010-07-29
申请号：DE102004063025
申请日：2004-12-22
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE-AUG , JUNG TAE-WOO , KIM SEON-MIN , KIM WOO-JIN , PARK HYUNG-SOON , KIM YOUNG-BOG , YANG HONG-SEON , SOHN HYUN-CHUL , HWANG EUNG-RIM
IPC分类号： H01L27/105 , H01L21/8239

4. 发明专利

DE102004063690B4 未知
公开(公告)号：DE102004063690B4
公开(公告)日：2010-02-11
申请号：DE102004063690
申请日：2004-12-28
申请人： HYNIX SEMICONDUCTOR INC
发明人： LIM KWAN-YONG , CHO HEUNG-JAE , KIM YONG-SOO , JANG SE-AUG , SOHN HYUN-CHUL
IPC分类号： H01L27/115 , G11C16/02 , H01L21/8247
摘要： A non-volatile memory device comprises a pair of conductive sidewall spacers (29B), for trapping/detrapping charges formed on a pair of sidewall spacers (28A). A non-volatile memory device comprises a gate insulation layer (22A) formed on a substrate (21); a gate structure (100) formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed below the sidewalls of the gate structure; and a pair of source/drain regions (30) formed in the substrate disposed below edge portions of the pair of conductive sidewall spacers. An independent claim is also included for a method of fabricating a non-volatile memory device, comprising forming a gate insulation layer on a substrate; forming a gate structure on the gate insulation layer; forming a pair of lightly doped drain regions in the substrate disposed below sidewalls of the gate structure; forming a pair of re-oxidation sidewall spacers (27) on sidewalls of the gate structure; simultaneously forming a pair of sidewall spacers and a pair of conductive sidewall spacers on the pair of re-oxidation sidewall spacers; and forming a pair of source/drain regions formed in the substrate disposed below edge portions of the pair of conductive sidewall spacers, and connected with the respective lightly doped drain regions.

5. 发明专利

DE102004063690A1 Non-volatile memory device e.g. flash memory for mobile communication system and memory card for storing music, comprises pair of conductive sidewall spacers for trapping/detrapping charges formed, on pair of sidewall spacers 未知
公开(公告)号：DE102004063690A1
公开(公告)日：2006-04-06
申请号：DE102004063690
申请日：2004-12-28
申请人： HYNIX SEMICONDUCTOR INC
发明人： LIM KWAN-YONG , CHO HEUNG-JAE , KIM YONG-SOO , JANG SE-AUG , SOHN HYUN-CHUL
IPC分类号： H01L27/115 , G11C16/02 , H01L21/8247
摘要： A non-volatile memory device comprises a pair of conductive sidewall spacers (29B), for trapping/detrapping charges formed on a pair of sidewall spacers (28A). A non-volatile memory device comprises a gate insulation layer (22A) formed on a substrate (21); a gate structure (100) formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed below the sidewalls of the gate structure; and a pair of source/drain regions (30) formed in the substrate disposed below edge portions of the pair of conductive sidewall spacers. An independent claim is also included for a method of fabricating a non-volatile memory device, comprising forming a gate insulation layer on a substrate; forming a gate structure on the gate insulation layer; forming a pair of lightly doped drain regions in the substrate disposed below sidewalls of the gate structure; forming a pair of re-oxidation sidewall spacers (27) on sidewalls of the gate structure; simultaneously forming a pair of sidewall spacers and a pair of conductive sidewall spacers on the pair of re-oxidation sidewall spacers; and forming a pair of source/drain regions formed in the substrate disposed below edge portions of the pair of conductive sidewall spacers, and connected with the respective lightly doped drain regions.

6. 发明专利

DE102004063025A1 未知
公开(公告)号：DE102004063025A1
公开(公告)日：2006-03-23
申请号：DE102004063025
申请日：2004-12-22
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE-AUG , JUNG TAE-WOO , KIM SEON-MIN , KIM WOO-JIN , PARK HYUNG-SOON , KIM YOUNG-BOG , YANG HONG-SEON , SOHN HYUN-CHUL , HWANG EUNG-RIM
IPC分类号： H01L27/105 , H01L21/8239
摘要： Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

7. 发明专利

DE102004057978A1 Fabrication of semiconductor device with dual dielectric structure, e.g. non-volatile dynamic random access memory device, includes forming oxide layer by radical oxidation process 未知
公开(公告)号：DE102004057978A1
公开(公告)日：2006-01-26
申请号：DE102004057978
申请日：2004-11-30
申请人： HYNIX SEMICONDUCTOR INC
发明人： CHO HEUNG-JAE , JANG SE-AUG , LIM KWAN-YONG , OH JAE-GEUN , YANG HONG-SEON , SOHN HYUN-CHUL
IPC分类号： H01L21/8247
摘要： Fabrication of semiconductor device with a dual dielectric structure includes forming insulation layer and nitride layer on substrate, selectively etching nitride layer in predetermined region of substrate, performing radical oxidation process to form oxide layer, forming gate conductive layer, and performing selective etching process to gate conductive layer, oxide layer, nitride layer and insulation layer. Fabrication of semiconductor device with a dual dielectric structure includes forming an insulation layer (502) and a nitride layer sequentially on a substrate (500); selectively etching the nitride layer in a predetermined region of the substrate; performing radical oxidation process to form an oxide layer (505) on the insulation layer and the etched nitride layer; forming a gate conductive layer (506) on the oxide layer; and performing selective etching process to the gate conductive layer, oxide layer, nitride layer and insulation layer, so that a first dielectric structure formed in the predetermined region includes the insulation layer and oxide layer, and a second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, nitride layer and oxide layer.

8. 发明专利

DE102004020157A1 Capacitor for semiconductor devices, has lower electrode, upper electrode, and dielectric layer with portion formed by alloying hafnium oxide and aluminum oxide together 未知
公开(公告)号：DE102004020157A1
公开(公告)日：2005-06-23
申请号：DE102004020157
申请日：2004-04-24
申请人： HYNIX SEMICONDUCTOR INC
发明人： KIL DEOK-SIN , ROH JAE-SUNG , SOHN HYUN-CHUL
IPC分类号： H01L21/02 , H01L21/28 , H01L21/314 , C23C16/40 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/08 , H01L27/105 , H01L27/108 , H01L29/76 , H01L31/062
摘要： A capacitor comprises a lower electrode (21), a dielectric layer formed on the lower electrode, and an upper electrode (23) formed on the dielectric layer. A portion of the dielectric layer contacting one of the lower and upper electrodes is formed by alloying hafnium oxide (22B) and aluminum oxide (22A) together. An independent claim is also included for a method of fabricating a capacitor, comprising: forming a lower electrode; forming a dielectric layer alloyed with hafnium oxide and aluminum oxide on the lower electrode; and forming an upper electrode on the dielectric layer.

9. 发明专利

JP2006108620A Nonvolatile memory device containing conductive side wall spacer and its manufacturing method 审中-公开
标题翻译：包含导电侧壁间隔件的非易失性存储器件及其制造方法
公开(公告)号：JP2006108620A
公开(公告)日：2006-04-20
申请号：JP2005114834
申请日：2005-04-12
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： LIM KWAN YONG , CHO KOZAI , KIM YONG-SOO , JANG SE AUG , SOHN HYUN-CHUL
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7887 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L29/66825 , H01L29/788
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device containing a conductive side wall spacer compatible with improvement of deterioration in reliability for the case of utilizing a conventional nitride film side wall for a charge trap medium, and to provide a method for manufacturing it.
SOLUTION: This nonvolatile memory device containing a conductive side wall spacer comprises a semiconductor substrate 21; a gate insulating film 22A on the semiconductor substrate; a gate 100 formed on the gate insulating film; a pair of side wall spacers 28A of insulating film formed on both side wall of the gate; a pair of conductive side wall spacers 29B formed on the pair of side wall spacers to capture and discharge charges; a pair of LDD regions 26 formed in the semiconductor substrate under both the side wall of the gate, a pair of the side wall spacers and the conductive side wall spacers; and a source/drain region 30 formed in the semiconductor substrate under an external region containing an external edge of a pair of the conductive side wall spacer on both sides of the gate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种非易失性存储装置，其包含导电侧壁间隔物，其与利用传统的电荷捕获介质的氮化物膜侧壁的情况相一致可改善劣化的可靠性，并提供一种方法制造它。包含导电侧壁间隔物的非易失性存储器件包括半导体衬底21; 半导体基板上的栅极绝缘膜22A; 形成在栅极绝缘膜上的栅极100; 形成在门的两侧壁上的一对绝缘膜的侧壁间隔件28A; 一对导电侧壁间隔件29B，其形成在所述一对侧壁间隔件上以捕获和放电电荷; 形成在半导体衬底中的栅极侧壁，一对侧壁间隔物和导电侧壁间隔物之间的一对LDD区域26; 以及源极/漏极区域30，其形成在半导体衬底内的外部区域，该外部区域包含栅极两侧的一对导电侧壁间隔物的外部边缘。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2006041475A Memory device and its manufacturing method 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：JP2006041475A
公开(公告)日：2006-02-09
申请号：JP2005114921
申请日：2005-04-12
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： JANG SE AUG , TEI DAIGU , KIM SEO-MIN , KIM WOO-JIN , PARK HYUNG-SOON , KIM YOUNG-BOG , YANA KOUZEN , SOHN HYUN-CHUL , HWANG EUNG-RIM
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78
CPC分类号： H01L27/11521 , H01L27/10855 , H01L27/10888 , H01L27/115 , H01L29/7886
摘要： PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold time of the memory device. SOLUTION: The memory device comprises a semiconductor substrate (610) with a recess (600) formed therein, a first junction region (670A) formed on a surface lower part of the semiconductor substrate in the recess, a plurality of second junction regions (670B) formed on a surface lower part of the semiconductor substrate outside the recess, gate structures (655) formed on the semiconductor substrate between the first and second junction regions, including at least a part of the gate structure formed on the semiconductor substrate in the recess, a first contact plug (690A) formed on the first junction region by burying between the gate structures, and a plurality of second plugs (690B) formed on the second junction regions by burying between the gate structures. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种通过防止短路效应来调节存储器件的阈值电压的存储器件及其制造方法，并且减小在存储节点结区域中产生的结漏电流，从而增加存储器件的数据保持时间。解决方案：存储器件包括其中形成有凹部（600）的半导体衬底（610），形成在凹部中的半导体衬底的表面下部的第一接合区域（670A），多个第二接合部形成在凹部外部的半导体衬底的表面下部的区域（670B），形成在第一和第二结区之间的半导体衬底上的栅极结构（655），其包括形成在半导体衬底上的栅极结构的至少一部分在所述凹部中，通过掩埋所述栅极结构而形成在所述第一接合区域上的第一接触插塞（690A）和通过掩埋所述栅极结构之间形成在所述第二接合区域上的多个第二插塞（690B）。版权所有（C）2006，JPO＆NCIPI

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