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1. 发明专利

JP2008091868A Method of forming recess gate of semiconductor element 审中-公开
标题翻译：形成半导体元件的阻挡门的方法
公开(公告)号：JP2008091868A
公开(公告)日：2008-04-17
申请号：JP2007176894
申请日：2007-07-05
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： JANG SE AUG , CHO KOZAI , KIN TAIJUN
IPC分类号： H01L29/78 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66553 , H01L27/10823 , H01L27/10876 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a recess gate of a semiconductor element, capable of preventing damage of an active region, even if a loss of a field oxide film below a path gate and overlay misalignment occur between the active region and a recess pattern in forming the recess gate.
SOLUTION: The method includes a step of forming a field oxide film 22 for defining the active region 23 on a semiconductor substrate 21; a step of forming a hard mask pattern 24A for selectively exposing at least a part of the active region 23 on the substrate 21; a step of performing etching using the hard mask pattern 24A as an etching barrier to form recess patterns 29 on the active region 23; a step of removing the hard mask pattern 24A; a step of forming a gate insulating film on the substrate 21 having the recess patterns 29 formed thereon; and a step of forming a gate electrode for covering at least the recess patterns 29 on the gate insulating film.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了提供能够防止有源区域的损坏的半导体元件的凹槽的制造方法，即使在路径栅极以下的场氧化膜的损失和覆盖不对中，活性区域和形成凹槽的凹陷图案。解决方案：该方法包括在半导体衬底21上形成用于限定有源区23的场氧化膜22的步骤; 形成用于选择性地暴露基板21上的有源区23的至少一部分的硬掩模图案24A的步骤; 使用硬掩模图案24A作为蚀刻阻挡层进行蚀刻以在有源区域23上形成凹部图案29的步骤; 去除硬掩模图案24A的步骤; 在其上形成凹部图案29的基板21上形成栅极绝缘膜的步骤; 以及形成用于至少覆盖栅极绝缘膜上的凹部图案29的栅电极的步骤。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006313869A Manufacturing method of transistor of semiconductor memory element 有权
标题翻译：半导体存储器元件晶体管的制造方法
公开(公告)号：JP2006313869A
公开(公告)日：2006-11-16
申请号：JP2005178793
申请日：2005-06-20
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： JANG SE AUG , KIM YONG-SOO , OH JAE GEUN
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7851 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/66795
摘要： PROBLEM TO BE SOLVED: To provide a transistor manufacturing method of a semiconductor memory element which can reduce the difficulty of a manufacturing process by restraining generation of void in formation of a low resistance gate electrode.
SOLUTION: The method comprises a step for etching a semiconductor substrate 1 and forming an active region 1a projecting from the semiconductor substrate 1, a step for forming a field oxide film 2 in a periphery thereof, a step for forming a first recess groove g1 of a depth d1 in a channel region inside the active region 1a, a step for forming a second recess groove g2 of a depth d2 by etching a portion of the field oxide film 2 making a gate electrode pass through more deeply than the first recess groove, a step for forming a gate insulating film on the upper surface of the active region 1a and the surface of the active region 1a exposed by the first and second recess grooves g1, g2, and a step for forming a gate electrode on the field oxide film 2 including the gate insulating film being superposed on the first and second recess grooves g1, g2 to cross above the active region 1a.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储元件的晶体管制造方法，其可以通过抑制在形成低电阻栅电极时产生空隙而降低制造工艺的难度。解决方案：该方法包括用于蚀刻半导体衬底1并形成从半导体衬底1突出的有源区1a的步骤，在其周边形成场氧化物膜2的步骤，用于形成第一凹部在有源区域1a内的沟道区域内具有深度d1的槽g1，通过蚀刻场氧化膜2的一部分形成深度为d2的第二凹槽g2的步骤，使得栅电极比第一凹槽，用于在有源区域1a的上表面上形成栅极绝缘膜的步骤和由第一和第二凹槽g1，g2暴露的有源区域1a的表面，以及用于在栅极电极上形成栅电极的步骤包括栅极绝缘膜的场氧化物膜2叠置在第一和第二凹槽g1，g2上，以跨越有源区域1a上方。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2008091917A Semiconductor element provided with bulb-type recessed channel, and its manufacturing method 审中-公开
标题翻译：带有BULB型接收通道的半导体元件及其制造方法
公开(公告)号：JP2008091917A
公开(公告)日：2008-04-17
申请号：JP2007254779
申请日：2007-09-28
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KIM YONG-SOO , YANA KOUZEN , JANG SE AUG , PYI SEUNG HO , KO KEN , CHO KOZAI , LIM KWAN-YONG , SUNG MIN-GYU , LEE SEUNG-RYONG , KIN TAIJUN
IPC分类号： H01L29/78 , H01L29/417
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/518 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element provided with a bulb-type recessed channel which can prevent growth and move of a void produced inside a ball pattern when a conductive film used as a gate electrode is formed, and to provide its manufacturing method.
SOLUTION: The method for manufacturing the semiconductor element includes: a step for forming bulb-type recessed regions 24 and 26 on a substrate; a step for forming a gate insulating film 27 on the substrate 21B on which the bulb-type recessed regions 24 and 26 are formed; and a step for forming gate conductive films 28A and 29, which are constituted by two or more conductive films while having a discontinuous interface 30 between these conductive films, on the gate insulating film 27, to bury the bulb-type recessed regions 24 and 26.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有灯泡型凹槽的半导体元件，当形成用作栅电极的导电膜时，可以防止在球形图案内产生的空隙的生长和移动，并且提供其制造方法。解决方案：制造半导体元件的方法包括：在基板上形成灯泡型凹陷区域24和26的步骤; 在形成有灯泡型凹部区域24,26的基板21B上形成栅极绝缘膜27的工序; 以及用于形成栅极导电膜28A和29的步骤，其由两个或更多个导电膜构成，同时在这些导电膜之间具有不连续的界面30，在栅极绝缘膜27上，以埋置灯泡型凹入区域24和26 版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008091905A METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT WITH FinFET 审中-公开
标题翻译：使用FinFET制造半导体元件的方法
公开(公告)号：JP2008091905A
公开(公告)日：2008-04-17
申请号：JP2007247607
申请日：2007-09-25
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： JANG SE AUG , YANA KOUZEN , AHN TAE-HANG
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/108 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L29/66795 , H01L29/7851
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a FinFET which can prevent loss of an element isolation film and improve current driving capability without causing deterioration of off-leakage characteristic, even if three faces working as a channel of a fin active region pattern are released.
SOLUTION: The method includes a step of forming an element isolation film 22 for defining adjacent active regions 23 on a semiconductor substrate 21; a step of exposing a region having an active region pattern 29B to be formed and forming a hard mask pattern for covering an element isolation film 22 between the regions; a step of selectively forming a recess 29A on the element isolation film 22 on the exposed region using the hard mask as an etching barrier, and forming the active region pattern 29B; a step of removing the hard mask pattern; a step of forming a gate insulating film on the semiconductor substrate 21; and a step of forming a gate electrode for covering the active region pattern 29B on the gate insulating film.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种可以防止元件隔离膜损耗并且提高电流驱动能力而不引起泄漏特性恶化的FinFET的制造方法，即使作为鳍的通道的三个面活动区域模式被释放。解决方案：该方法包括形成用于限定半导体衬底21上的相邻有源区23的元件隔离膜22的步骤; 暴露具有要形成的有源区域图案29B的区域并形成用于覆盖区域之间的元件隔离膜22的硬掩模图案的步骤; 使用硬掩模作为蚀刻阻挡层在曝光区域上的元件隔离膜22上选择性地形成凹部29A的步骤，形成有源区域图案29B; 去除硬掩模图案的步骤; 在半导体基板21上形成栅极绝缘膜的工序; 以及形成用于覆盖栅极绝缘膜上的有源区域图案29B的栅电极的步骤。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007258743A Method of forming gate electrode in semiconductor device 有权
标题翻译：在半导体器件中形成门电极的方法
公开(公告)号：JP2007258743A
公开(公告)日：2007-10-04
申请号：JP2007141320
申请日：2007-05-29
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： JANG SE AUG , YEO IN SEOK
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode in a semiconductor device, which can prevent abnormal oxidation of a titanium silicide film when the surface of a gate electrode consisting of a doped polysilicon film and the titanium silicide film is re-oxidized. SOLUTION: The method includes the steps of: forming a gate oxide film and a polysilicon film on a semiconductor substrate; depositing a first TiSix film on the polysilicon film; depositing a silicon film on the first TiSix film; depositing a second TiSix film on the silicon film; performing thermal treatment to form an TiSi 2 film in a silicon-rich state from the first TiSix film, the silicon film, and the second TiSix film; depositing an insulating film on the TiSi 2 film; patterning the insulating film, TiSi 2 film, polysilicon film, and gate oxide film to form a gate electrode having a laminated structure of TiSi 2 film and the polysilicon film; and performing gate re-oxidation. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在半导体器件中形成栅电极的方法，其可以防止当由掺杂多晶硅膜和硅化钛膜组成的栅电极的表面时硅化钛膜的异常氧化被再氧化。解决方案：该方法包括以下步骤：在半导体衬底上形成栅极氧化膜和多晶硅膜; 在多晶硅膜上沉积第一TiSix膜; 在第一TiSix膜上沉积硅膜; 在硅膜上沉积第二TiSix膜; 进行热处理，从第一TiSix膜，硅膜和第二TiSix膜形成富硅状态的TiSi 2 SBS膜; 在TiSi 2薄膜上沉积绝缘膜; 图案化绝缘膜，TiSi SB 2膜，多晶硅膜和栅极氧化物膜，以形成具有TiSi 2 SiO 2层叠结构的栅电极和多晶硅膜; 并执行栅极再氧化。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2006310749A Manufacturing method for transistor used for semiconductor element 审中-公开
标题翻译：用于半导体元件的晶体管的制造方法
公开(公告)号：JP2006310749A
公开(公告)日：2006-11-09
申请号：JP2005367141
申请日：2005-12-20
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： KIM MYUNG-OK , TEI DAIGU , LEE SUNG-KWON , JANG SE AUG
IPC分类号： H01L29/78 , H01L21/3065 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/31116 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a transistor capable of improving refreshing characteristics of an element and used for a semiconductor element.
SOLUTION: The method includes a first step in which an active region 12 is demarcated by forming an element isolation film 11 to a silicon substrate 10 provided with a prescribed lower structure, a second step for forming a recess 17 with a relatively flat bottom having a larger CD than that of the upper part by etching the active region 12 to a prescribed depth, a third step for forming a gate oxide film and a metal film in turn on the surface of the recess 17 by vapor deposition, and a fourth step for forming a gate electrode by patterning the gate oxide film and the metal film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够改善元件的刷新特性并用于半导体元件的晶体管的制造方法。解决方案：该方法包括第一步骤，其中通过在具有规定的下部结构的硅衬底10上形成元件隔离膜11来界定有源区域12，第二步骤用于形成具有相对平坦的凹部17 通过将有源区12蚀刻到规定的深度，具有比上部更大的CD的底部，用于通过气相沉积在凹部17的表面上依次形成栅氧化膜和金属膜的第三步骤，以及通过图案化栅极氧化膜和金属膜来形成栅电极的第四步骤。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006310718A Transistor structure of memory device and its manufacturing method 审中-公开
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：JP2006310718A
公开(公告)日：2006-11-09
申请号：JP2005188007
申请日：2005-06-28
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： JANG SE AUG , KIM YONG-SOO , OH JAE-GEUN , RO SAISEI , SOHN HYUN-CHUL
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： PROBLEM TO BE SOLVED: To provide a transistor structure of a memory device in a new form, and to provide the manufacturing method of the transistor structure.
SOLUTION: The transistor is provided with an active region 111a projected from a prescribe region of a substrate 111, a recessed groove (g) formed in a channel region in the active region, a field oxide film 112 which is formed on the substrate around the active region and has a surface positioned lower than the upper face of the active region comprising the recessed groove, gate insulating films 113 formed in the recessed groove and on the active region whose surface is exposed and a gate electrode 114 which is overlapped with the recessed groove, crosses on the active region, and extends. An X-X' cross-section along source and drain lines is a recess transistor structure, and a Y-Y' cross-section along a gate line is a projected transistor structure.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供新形式的存储器件的晶体管结构，并提供晶体管结构的制造方法。晶体管设置有从基板111的规定区域突出的有源区域111a，形成在有源区域的沟道区域中的凹槽（g），形成在有源区域中的场氧化物膜112 衬底围绕有源区并且具有位于比包括凹槽的有源区的上表面更低的表面，形成在凹槽中的栅极绝缘膜113和其表面被暴露的有源区和重叠的栅电极114 具有凹槽，在有源区上交叉并延伸。沿着源极和漏极线的X-X'横截面是凹陷晶体管结构，并且沿着栅极线的Y-Y'截面是投射的晶体管结构。版权所有（C）2007，JPO＆INPIT

8. 发明专利

DE102005031702B4 Transistorstruktur eines Speicherbauelements und Verfahren zur Herstellung desselben 未知
公开(公告)号：DE102005031702B4
公开(公告)日：2012-06-21
申请号：DE102005031702
申请日：2005-07-05
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE AUG , KIM YONG SOO , OH JAE GEUN , ROH JAE SUNG , SOHN HYUN CHUL
IPC分类号： H01L29/78 , H01L21/8239 , H01L27/108
摘要： Speicherbauelement mit einem Transistor, wobei die Transistorstruktur aufweist: einen sich von einem vorbestimmten Abschnitt eines Halbleitersubstrats (111) erstreckender aktiven Bereich (111a); eine in einem in dem aktiven Bereich (111a) vorgesehenen Kanalbereich ausgebildete Ausnehmung (g); eine über dem Halbleitersubstrat (111) gebildete Feldoxidschicht (112), wobei die Feldoxidschicht (112) niedriger positioniert ist als eine obere Oberfläche des aktiven Bereichs (111a) einschließlich der Ausnehmung (g); eine sich über einen oberen Abschnitt des aktiven Bereichs (111a) erstreckende und die Ausnehmung (g) überlappende Gate-Elektrode; eine zwischen der Gate-Elektrode und dem aktiven Bereich (111a) angeordnete Gate-Isolationsschicht (113); und Source- und Drain Bereiche, jeweils in dem aktiven Bereich (111a) an einer Seite der Gate-Elektrode ausgebildet.

9. 发明专利

DE102005028640B4 未知
公开(公告)号：DE102005028640B4
公开(公告)日：2010-06-02
申请号：DE102005028640
申请日：2005-06-20
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE AUG , KIM YONG SOO , OH JAE GEUN
IPC分类号： H01L21/336 , H01L21/8239
摘要： Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

10. 发明专利

DE102005031702A1 Memory device e.g. dynamic random access memory, has transistor such as recessed transistor and fin transistor, with active area protruding from preset portion of semiconductor substrate, and recess formed in channel area 未知
公开(公告)号：DE102005031702A1
公开(公告)日：2006-11-02
申请号：DE102005031702
申请日：2005-07-05
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE AUG , KIM YONG SOO , OH JAE GEUN , ROH JAE SUNG , SOHN HYUN CHUL
IPC分类号： H01L27/105 , H01L21/8239
摘要： The device has a transistor such as a recessed transistor and a fin transistor, with an active area (111a) protruding from a preset portion of a semiconductor substrate (111), and a recess formed in a channel area provided in the active area. A field oxide layer is formed over the substrate, and a gate electrode is extended across an upper portion of the active area and overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area, and source and drain areas are formed in the active area at sides of the gate electrode. An independent claim is also included for a method for fabricating a semiconductor memory device.

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