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1. 发明专利

DE102004063025B4 Speicherbauelement und Verfahren zur Herstellung desselben 未知
公开(公告)号：DE102004063025B4
公开(公告)日：2010-07-29
申请号：DE102004063025
申请日：2004-12-22
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE-AUG , JUNG TAE-WOO , KIM SEON-MIN , KIM WOO-JIN , PARK HYUNG-SOON , KIM YOUNG-BOG , YANG HONG-SEON , SOHN HYUN-CHUL , HWANG EUNG-RIM
IPC分类号： H01L27/105 , H01L21/8239

2. 发明专利

DE102004063025A1 未知
公开(公告)号：DE102004063025A1
公开(公告)日：2006-03-23
申请号：DE102004063025
申请日：2004-12-22
申请人： HYNIX SEMICONDUCTOR INC
发明人： JANG SE-AUG , JUNG TAE-WOO , KIM SEON-MIN , KIM WOO-JIN , PARK HYUNG-SOON , KIM YOUNG-BOG , YANG HONG-SEON , SOHN HYUN-CHUL , HWANG EUNG-RIM
IPC分类号： H01L27/105 , H01L21/8239
摘要： Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

3. 发明专利

JP2006041475A Memory device and its manufacturing method 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：JP2006041475A
公开(公告)日：2006-02-09
申请号：JP2005114921
申请日：2005-04-12
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： JANG SE AUG , TEI DAIGU , KIM SEO-MIN , KIM WOO-JIN , PARK HYUNG-SOON , KIM YOUNG-BOG , YANA KOUZEN , SOHN HYUN-CHUL , HWANG EUNG-RIM
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/78
CPC分类号： H01L27/11521 , H01L27/10855 , H01L27/10888 , H01L27/115 , H01L29/7886
摘要： PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold time of the memory device. SOLUTION: The memory device comprises a semiconductor substrate (610) with a recess (600) formed therein, a first junction region (670A) formed on a surface lower part of the semiconductor substrate in the recess, a plurality of second junction regions (670B) formed on a surface lower part of the semiconductor substrate outside the recess, gate structures (655) formed on the semiconductor substrate between the first and second junction regions, including at least a part of the gate structure formed on the semiconductor substrate in the recess, a first contact plug (690A) formed on the first junction region by burying between the gate structures, and a plurality of second plugs (690B) formed on the second junction regions by burying between the gate structures. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种通过防止短路效应来调节存储器件的阈值电压的存储器件及其制造方法，并且减小在存储节点结区域中产生的结漏电流，从而增加存储器件的数据保持时间。解决方案：存储器件包括其中形成有凹部（600）的半导体衬底（610），形成在凹部中的半导体衬底的表面下部的第一接合区域（670A），多个第二接合部形成在凹部外部的半导体衬底的表面下部的区域（670B），形成在第一和第二结区之间的半导体衬底上的栅极结构（655），其包括形成在半导体衬底上的栅极结构的至少一部分在所述凹部中，通过掩埋所述栅极结构而形成在所述第一接合区域上的第一接触插塞（690A）和通过掩埋所述栅极结构之间形成在所述第二接合区域上的多个第二插塞（690B）。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2003332571A Method for manufacturing semiconductor element 有权
标题翻译：制造半导体元件的方法
公开(公告)号：JP2003332571A
公开(公告)日：2003-11-21
申请号：JP2002368921
申请日：2002-12-19
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： KIM JAE-OK , KIM WOO-JIN , OH JONG-HYUK
IPC分类号： H01L29/423 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28061 , H01L29/4933 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element suitable for suppressing stress concentrating on lower corners of a gate electrode while preventing the oxidation of metal contained in a gate electrode. SOLUTION: This method for manufacturing a semiconductor element comprises a step for forming a gate oxide film on a semiconductor substrate, a step for forming a gate electrode containing at least one metal film on the gate oxide film, a step for forming the oxide film at a temperature which is lower than the oxidation temperature of the metal film on the whole face of the semiconductor substrate containing the gate electrode, and a step for selectively etching the dense oxide film, and for forming an oxide film spacer on the sidewall of the gate electrode. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种制造半导体元件的方法，该半导体元件适用于抑制集中在栅电极的下角上的应力，同时防止栅电极中所含金属的氧化。解决方案：这种半导体元件的制造方法包括在半导体基板上形成栅极氧化膜的工序，在栅极氧化膜上形成含有至少一层金属膜的栅电极的工序，形成工序氧化膜的温度低于包含栅电极的半导体衬底的整个表面上的金属膜的氧化温度的温度，以及用于选择性地蚀刻致密氧化膜并在侧壁上形成氧化膜间隔物的步骤的栅电极。版权所有（C）2004，JPO

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