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1. 发明专利

JPS6080268A MANUFACTURE OF SEMICONDUCTOR IC DEVICE 失效
公开(公告)号：JPS6080268A
公开(公告)日：1985-05-08
申请号：JP18691683
申请日：1983-10-07
申请人： HITACHI MICROCUMPUTER ENG , AKITA DENSHI KK , HITACHI LTD
发明人： TAKIGAWA AKIRA , INABA TOORU , KOWASE YASUAKI , TAKAGI SHINICHI , IHARA HIROSHI
IPC分类号： H01L21/331 , H01L21/761 , H01L21/8226 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To obtain the titled device with improved characteristics by a method wherein, in providing the same semiconductor substrate with a bi-polar transistor element and an I L element, the semiconductor layer is thinned by the boring of a groove at the middle of the layer, where an isolation region is formed and then shallowed more than the depth of the base region of the bi-polar element. CONSTITUTION:Two N type buried region 13 are diffusion-formed in the surface layer part of the P type Si substrate 10, and an N type layer 12 is epitaxially grown over the entire surface including the regions, the parts of which layer containing the regions are then used as a bi-polar transistor element Q1 region a1 and an I L element region a2, respectively. Next, a wide groove 16 is bored between these regions, and a narrow groove 14 outside the regions; an insulation film is adhered over the entire surface, and an aperture is provided in the groove 14, and an aperture of the same size of that of the groove 14 in the groove 16. Thereafter, P type impurity ions are implanted therein, and next elongating diffusion is carried out, resulting in the formation of the P type isolation region 20 at a low level reaching the substrate. Accordingly, this region is shallowed more than the depths of a P type base region 22 and a graft structural base region 32.

2. 发明专利

JPS60224229A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60224229A
公开(公告)日：1985-11-08
申请号：JP7856684
申请日：1984-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TEZUKA IZUMI , SAKURAI SHIYUUICHI , INABA TOORU , MATSUMOTO MASATO
IPC分类号： H01L23/522 , H01L21/31 , H01L21/312 , H01L21/768
摘要： PURPOSE:To stop decreasing of moisture resistance due to the influence of phosphorus to the first wiring layer without altering the present process by forming the first layer wiring of wirings through an inorganic insulating film containing no phosphorus on an inorganic insulating film which contains phosphorus oxide glass layer on the surface. CONSTITUTION:A glass (PSG) film 7 which contains high density phosphorus oxide is formed on the surface of a silicon oxide 2 for coating the surface of a semiconductor element formed on the other portion of the surface of a substrate 1. An inorganic insulating film 8 which does not contains phosphorus, formed on the film 7 is made, for example, of glass (SOG) by coating and silicon oxide by CVD not doped with nitride or phosphorus due to plasma discharging. The first layer wirings made of aluminum are formed as an electrode contacted with low resistance with the element, and partly extended on the film 8.

3. 发明专利

JPS615563A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS615563A
公开(公告)日：1986-01-11
申请号：JP12524684
申请日：1984-06-20
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIKAWA TAKAYOSHI , INABA TOORU , TAKAGI TATSUHAYA , KOWASE YASUAKI , HIRASHIMA TOSHINORI
IPC分类号： H01L27/00 , H01L21/312 , H01L27/06
摘要： PURPOSE:To facilitate the installation of upper elements and to increase freedom in the arrangement of elements by a method wherein a polyimide film is formed to flatten an insulating film with its surface rendered uneven due to lower-stage semiconductor elements in a three-dimensional structure wherein elements on a substrate are arranged in a plurality of stages. CONSTITUTION:On a quartz substrate 1, Mo electrodes 2a, 2b, 2c, SiO2 film 3, a-Si film 4, and Al electrodes 5a, 5b... are formed. Next, an SiO2 film 6 is formed, followed by an a-Si film 7 and Mo electrode 8. A polyimide film 9 is formed, which fills up the recesses in the SiO2 film 6 for the realization of a flattened surface. Etching is performed for the exposure of the a-Si film 7, and windows are provided for the electrodes 5a, 5d. A gate film 12a and Al electrodes 13a, 13b... are formed for the completion of a three-dimensional inverter circuit.

4. 发明专利

JPS60187055A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60187055A
公开(公告)日：1985-09-24
申请号：JP4200484
申请日：1984-03-07
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： INABA TOORU , KOWASE YASUAKI , ICHIKAWA TAKAYOSHI , TAKARADA MASAO
IPC分类号： H01L21/8222 , H01L21/28 , H01L21/331 , H01L27/06 , H01L29/43 , H01L29/45 , H01L29/73 , H01L29/732
摘要： PURPOSE:To reduce the parasitic resistance of the active element to be formed on a semiconductor substrate by a method wherein a metal silicide layer is provided between the semiconductor substrate and the epitaxial layer located above the semiconductor substrate, and an electrode is picked up through the intermediary of said metal silicide layer. CONSTITUTION:A metal silicide layer 12 is formed between an epitaxial layer 14 and a semiconductor substrate 10. A diffusion layer 16 to be used for connection of an n type collector, a p type base diffusion layer 18 and an n type diffusion layer 20 are formed on said layer 14 respectively. Also, an Al electrode 24 is formed from above of an oxide film 22, and an npn bipolar transistor TRQ1 is formed using said electrode 24. At this point, the layer 16 is connected to the layer 12. As a result, the collector electrode is picked up through the intermediary of the layers 12 and 16. In this instance, the resistance value of the layer 12 is remarkably made lower than that of the diffusion layer and, besides, the layer 12 is provided on the lower side of the layer 14. As a result, the resistance of the TRQ1 which is in parasitic in series to the collector becomes very low, thereby enabling to improve the characteristics such as working speed and the like of the TRQ1.

5. 发明专利

JPS60126871A SEMICONDUCTOR PRESSURE-SENSITIVE DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60126871A
公开(公告)日：1985-07-06
申请号：JP23427683
申请日：1983-12-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SHIMIZU ISAO , INABA TOORU , SUDOU YOSHIAKI
IPC分类号： G01L9/00 , H01L29/84
摘要： PURPOSE:To adjust the flatness and thickness of a diaphragm thin section easily by forming a plurality of diffusion resistance layers as pressure-sensitive sections to one main surface of an silicon semiconductor base body and forming an indentation section to the other main surface of the base body so that the pressure-sensitive sections function as the thin diaphragm sections. CONSTITUTION:The ions of O2 or N2 are implanted to a diaphragm region in the surface 1A of a p type impurity doped high-resistivity silicon substrate 1 through a mask 5. An n type impurity doped-silicon crystal layer 6 is formed. p type diffusion resistance layers 7 are shaped in the diaphragm region while a required semiconductor region for an IC is also formed to a peripheral section. A film 8 consisting of an insulator is formed at that time. An indentation section 2 is dug to the back of the substrate through anisotropic etching to the back 1B of the substrate 1. The insulating film 8 shaped between the substrate 1 and the epitaxial layer 6 functions as an etching stopper and the depth of the indentation section 2 is controlled at that time, and a diaphragm with a required thin section is formed.

6. 发明专利

JPS6039847A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6039847A
公开(公告)日：1985-03-01
申请号：JP14652583
申请日：1983-08-12
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TEZUKA IZUMI , ISHII SHIGEO , YUGAWA KOUICHI , KONDOU SHIZUO , KUBO MUTSUO , KATOU TOKIO , INABA TOORU
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/88
摘要： PURPOSE:To improve the moisture resistance of a first-layer aluminum wiring, and to remove a disconnection due to corrosion of the wiring by forming both a first layer wiring and a second layer wiring by aluminum containing a different substance. CONSTITUTION:First layer wirings 3 are formed by patterning aluminum containing a substance such as silicon by approximately 2% on an oxide film 2, and a first-layer insulating film 4 is formed in thickness sufficiently coating the first layer wirings with polyimide resin. Second layer wirings 5 consisting of aluminum containing silicon are connected to the first layer wirings 3 through holes 6 partially bored to the first-layer insulating film 4. Accordingly, since both wiring use aluminum containing silicon, corrosion in the grain boundaries of aluminum in the first layer wirings in the peripheral section of a chip can be prevented, and a defective disconnection can be improved. The same effect can be obtained by mixing a proper amount of a metallic element, such as nickel, molybdenum, titanium, palladium, etc. as an impurity to be contained in aluminum.

7. 发明专利

JPS59231839A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS59231839A
公开(公告)日：1984-12-26
申请号：JP10571783
申请日：1983-06-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： INABA TOORU , TAKAGI TATSUITSU , KOWASE YASUAKI , TAKIGAWA AKIRA
IPC分类号： H01L25/18 , H01L23/02 , H01L23/16 , H01L23/31 , H01L23/50 , H01L25/065 , H01L25/07 , H01L23/28 , H01L23/48 , H01L25/04
摘要： PURPOSE:To obtain an airtightly sealed package of high reliability at low cost by a method wherein an airtightly sealing cover is connected directly according to an airtightly sealing material to the surface of a semiconductor chip at the whole surface or at the ring type part along the periphery thereof. CONSTITUTION:The back of a semiconductor chip 2 is fixed to the tab 1 of a lead frame, a cover 3 of ceramics, glass, Si, metal material, etc. is provided facing to the surface of the chip, and airtightly sealed by glass or solder, etc. 4 at the frame type part along the periphery of the cover plate. Outside lead- out leads 5 are soldered directly to junction pads 6 at the periphery of the semiconductor substrate, and the outer edges thereof are bent downward. The semiconductor substrate 2, the cover 3, a part of each lead 5 are sealed according to epoxy resin 7 as occasion demands. To support the whole surface of the cover 3 on the surface of the chip 2 by the airtightly sealing material 4 and to connect is also favorable. According to this construction, the surface of the semiconductor chip can be cut off completely from the outside by a simple method, and the device of high reliability can be obtained.

8. 发明专利

JPH0115142B2 失效
公开(公告)号：JPH0115142B2
公开(公告)日：1989-03-15
申请号：JP22618182
申请日：1982-12-24
申请人： HITACHI LTD
发明人： OGURA SADAO , INABA TOORU , TAKAGI TATSUTOSHI
IPC分类号： H01L23/522 , H01L21/768

9. 发明专利

JPS6058651A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6058651A
公开(公告)日：1985-04-04
申请号：JP16661283
申请日：1983-09-12
申请人： HITACHI LTD
发明人： KOWASE YASUAKI , INABA TOORU , KONDOU SHIZUO , MINAMIMURA EIJI , HIRASHIMA TOSHINORI
IPC分类号： H01L27/00 , H01L21/822 , H01L27/04 , H01L27/06 , H01L29/30 , H01L29/78 , H01L29/786
摘要： PURPOSE:To improve the integration degree by construction of the title device in three dimensions by a method wherein semiconductor elements such as a transistor are formed in the surface layer part of an Si substrate, an amorphous Si layer being grown thereon, and an MOSFET consisting of an insulation gate electrode and source and drain electrodes sandwiching it being then provided therein. CONSTITUTION:A P type base region 2 is diffusion-formed in the surface layer part of the N type Si substrate 1, an N type emitter region 3 being then provided therein, and Al electrode wirings 5 contacting the regions 2 and 3, respectively, being then adhered after adhesion of an SiO2 film 4 over the entire surface and then by boring apertures, which are then covered with an SiO2 film 6 into the transistor. Next, the amorphous Si layer 7 is deposited on the film 6, P type regions 8 serving as the source and drain being diffusion-formed in its surface layer, and an Al gate electrode 11 being then mounted between the regions 8 after adhesion of an SiO2 film 9 over the entire surface. Besides, apertures are bored in the film 9, and the regions 8 are provided with Al electrodes 10, respectively, resulting in the formation of an FET. Thus, the Si layer 7 is made to function as a variable resistance layer, and the transistor is controlled by variation in voltages impressed on the electrodes 11.

10. 发明专利

JPS59208851A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS59208851A
公开(公告)日：1984-11-27
申请号：JP8265483
申请日：1983-05-13
申请人： Hitachi Ltd
发明人： INABA TOORU
IPC分类号： H01L27/08 , H01L21/02 , H01L21/265 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76297
摘要： PURPOSE:To improve the density of integration by forming an insulating film on a side surface section isolating elements through the implantation of impurity ions and obtaining an isolation in an extremely narrow region. CONSTITUTION:A semiconductor substrate 1 is prepared, and an insulating film 13 consisting of SiO2 or Si3N4 obtained by combining O2 or N2 and Si is formed in predetermined depth by implanting impurity ions such as O2 or N2 to the whole surface on one main surface of the substrate and controlling the energy of the implantation. An impurity implantation control mask 2 is formed on the surface of a semiconductor substrate 1b. The impurity implantation control mask has an inclined section in its side surface, and impurity ions are implanted through the mask 2 to form insulating films 3a, 3b for isolating elements surrounding the bottoms and side surfaces of one semiconductor regions. Si gates 6, n type sources-drains 10 and p type sources-drains 8 are each shaped to the surfaces of each region in a self-alignment manner through selective diffusion.
摘要翻译：目的：通过在杂质离子的注入和在极窄的区域中获得隔离来在侧表面部隔离元件上形成绝缘膜来提高积分密度。构成：制备半导体衬底1，并且通过将O 2或N 2与Si结合而获得的由SiO 2或Si 3 N 4组成的绝缘膜13通过在诸如O 2或N 2之类的杂质离子注入到一个主表面上的整个表面上而以预定的深度形成底物并控制植入能量。在半导体衬底1b的表面上形成杂质注入控制掩模2。杂质注入控制掩模在其侧表面具有倾斜部分，并且通过掩模2注入杂质离子，以形成用于隔离围绕一个半导体区域的底部和侧表面的元件的绝缘膜3a，3b。 Si栅极6，n +型源极 - 漏极10和p +型源极 - 漏极8分别通过选择性扩散以自对准方式成形为每个区域的表面。

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