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1. 发明专利

JPS61194872A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61194872A
公开(公告)日：1986-08-29
申请号：JP3439885
申请日：1985-02-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： INABA TORU , KOWASE YASUAKI , ICHIKAWA TAKAYOSHI
IPC分类号： H01L21/761 , H01L21/331 , H01L21/76 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To prevent the latch-up by a method wherein a ring-shaped, P-type layer is formed so that it is connected from the surface of an N-type layer that is to be a base to a P-type embedded layer 11 that is to be a collector. CONSTITUTION:Resistors 7 and 8 consisting of P-type diffusion layers are formed within the island area surrounded by an isolation P-type layer 3, and the resistor 7 is directly connected to an external terminal PAD. A P-type, high-density embedded layer 11 is embedded in the bottom of an N-type layer 2b in the island area, contacting with a high-density N type embedded layer 4. A P-type layer 12 is formed so as to be connected to the layer 11 from the surface of the layer 2b, surrounding the resistor 7, and an electrode of the layer 12 is directly connected to the grounding electric potential GND. When the high voltage is applied from the terminal PAD to the layer 7, the surge electric power is left escape through the layer 12 to the grounding electric potential.

2. 发明专利

JPS615563A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS615563A
公开(公告)日：1986-01-11
申请号：JP12524684
申请日：1984-06-20
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： ICHIKAWA TAKAYOSHI , INABA TOORU , TAKAGI TATSUHAYA , KOWASE YASUAKI , HIRASHIMA TOSHINORI
IPC分类号： H01L27/00 , H01L21/312 , H01L27/06
摘要： PURPOSE:To facilitate the installation of upper elements and to increase freedom in the arrangement of elements by a method wherein a polyimide film is formed to flatten an insulating film with its surface rendered uneven due to lower-stage semiconductor elements in a three-dimensional structure wherein elements on a substrate are arranged in a plurality of stages. CONSTITUTION:On a quartz substrate 1, Mo electrodes 2a, 2b, 2c, SiO2 film 3, a-Si film 4, and Al electrodes 5a, 5b... are formed. Next, an SiO2 film 6 is formed, followed by an a-Si film 7 and Mo electrode 8. A polyimide film 9 is formed, which fills up the recesses in the SiO2 film 6 for the realization of a flattened surface. Etching is performed for the exposure of the a-Si film 7, and windows are provided for the electrodes 5a, 5d. A gate film 12a and Al electrodes 13a, 13b... are formed for the completion of a three-dimensional inverter circuit.

3. 发明专利

JPS60187055A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60187055A
公开(公告)日：1985-09-24
申请号：JP4200484
申请日：1984-03-07
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： INABA TOORU , KOWASE YASUAKI , ICHIKAWA TAKAYOSHI , TAKARADA MASAO
IPC分类号： H01L21/8222 , H01L21/28 , H01L21/331 , H01L27/06 , H01L29/43 , H01L29/45 , H01L29/73 , H01L29/732
摘要： PURPOSE:To reduce the parasitic resistance of the active element to be formed on a semiconductor substrate by a method wherein a metal silicide layer is provided between the semiconductor substrate and the epitaxial layer located above the semiconductor substrate, and an electrode is picked up through the intermediary of said metal silicide layer. CONSTITUTION:A metal silicide layer 12 is formed between an epitaxial layer 14 and a semiconductor substrate 10. A diffusion layer 16 to be used for connection of an n type collector, a p type base diffusion layer 18 and an n type diffusion layer 20 are formed on said layer 14 respectively. Also, an Al electrode 24 is formed from above of an oxide film 22, and an npn bipolar transistor TRQ1 is formed using said electrode 24. At this point, the layer 16 is connected to the layer 12. As a result, the collector electrode is picked up through the intermediary of the layers 12 and 16. In this instance, the resistance value of the layer 12 is remarkably made lower than that of the diffusion layer and, besides, the layer 12 is provided on the lower side of the layer 14. As a result, the resistance of the TRQ1 which is in parasitic in series to the collector becomes very low, thereby enabling to improve the characteristics such as working speed and the like of the TRQ1.

4. 发明专利

JPS6180849A Semiconductor integrated circuit device and manufacture thereof 失效
标题翻译：半导体集成电路器件及其制造
公开(公告)号：JPS6180849A
公开(公告)日：1986-04-24
申请号：JP20175784
申请日：1984-09-28
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKAGI TATSUHAYA , KOWASE YASUAKI , ICHIKAWA TAKAYOSHI , INABA TORU , KONDO SHIZUO
IPC分类号： H01L27/00 , H01L21/20 , H01L21/822 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/8221
摘要： PURPOSE:To constitute a three dimensional bipolar MOSIC by a method wherein a MOSFET composed of a bipolar type transistor as the first step semiconductor element and a channel made of amorphous silicon step semiconductor element respectively formed through the intermediary of an insulating film is formed on the surface of a semiconductor substrate. CONSTITUTION:An n type buried layer 2 is buried in a part of p type Si substrate 1 to grow an n type Si layer 3 epitaxially as well as to form isolated p type layer 4 by means of implanting B ion. Firstly impurity is diffused to form a p type base 5, an n type emitter 6 and an n type collector 7 as well as to provide an excellent electrode 8. Secondly an SiO2 film 9 is formed and etched to make recessions 11. Thirdly a-Si12 buried in the recessions 11 and doped with impurity is made into source . drain with low resistance n type conductivity. Fourthly another a-Si13 entirely doped with impurity is thinly formed. Fifthly p type impurity is diffused in the upper thin a a-Si film 13 to form an n or p type layer. Finally a thick CVD.SiO2 film 14 is formed to form another thin SiO2 film 15 as a gate further forming an electrode 16.
摘要翻译：目的：为了通过以下方法构成三维双极MOSIC：通过以下方法形成由双极型晶体管构成的MOSFET作为第一阶梯半导体元件，以及分别通过绝缘膜形成的由非晶硅步进半导体元件形成的沟道半导体衬底的表面。构成：n +型埋层2被埋在p型Si衬底1的一部分中，以外延生长n +型Si层3，并通过以下方式形成隔离的p型层4：植入B离子。首先，杂质扩散以形成p型基体5，n型发射极6和n +型集电体7，并提供优异的电极8.其次，形成SiO 2膜9并蚀刻以形成凹陷11.第三埋入凹陷11中并掺杂有杂质的a-Si12被制成源。漏极具有低电阻n +型导电性。第四，完全掺杂有杂质的另一个a-Si13被薄形成。第五，p +型杂质扩散到上薄的a-Si膜13中以形成n +或p +型层。最后，形成厚的CVDSiO 2膜14，以形成另一个薄的SiO 2膜15作为进一步形成电极16的栅极。

5. 发明专利

JPS60171775A FILTER FOR LIGHT-EMITTING ELEMENT 失效
公开(公告)号：JPS60171775A
公开(公告)日：1985-09-05
申请号：JP2708784
申请日：1984-02-17
申请人： HITACHI LTD
发明人： ICHIKAWA TAKAYOSHI , KOWASE YASUAKI , TAKARADA MASAO
IPC分类号： G02B5/22 , H01L33/14 , H01L33/20 , H01L33/30
摘要： PURPOSE:To obtain a filter for semiconductor light-emitting element, which has a superior selective absorptivity of wavelength and can be easily manufactured, by a method wherein some number of amorphous silicon films, each having a different absorption wavelength, are laminated on the transparent substrate. CONSTITUTION:Silicon elements including impurity elements 8 to make different absorption wavelengths on a rotary plate 7 are variously prepared in a sputter source 5 and the rotary plate 7 is made to revolve while the sputter source 5 is properly added in a furnace 6. By this way, thin amorphous silicon (a-Si) films 4, each having a different absorption wavelength, are laminated on a glass plate 3. Among impurity elements to be used for making different absorption wavelengths are such elements as N, Ge, Sn and so forth. An a-SiN film absorbs shorter wavelengths of 500nm or less, and an a-SiGe film and an a-SiSn film absorb longer wavelengths of 600-700nm or more. The a-Si filter which is obtained in such a way is installed on the luminous surface of a high luminance visible light-emitting diode, for example, and the filter absorbs unnecessary wavelengths and necessary wavelengths only are allowed to pass through.

6. 发明专利

JPH0556657B2 失效
公开(公告)号：JPH0556657B2
公开(公告)日：1993-08-20
申请号：JP14238684
申请日：1984-07-11
申请人： HITACHI LTD , HITACHI MICRO SYSTEM KK
发明人： KOWASE YASUAKI , ICHIKAWA TAKAYOSHI , TAKAGI TATSUTOSHI , AKAMATSU YOSHINORI , ISHIKAWA MAKOTO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L23/522 , H01L23/556 , H01L23/60 , H01L23/62

7. 发明专利

JPS6123353A Over voltage protection element 失效
标题翻译：过电压保护元件
公开(公告)号：JPS6123353A
公开(公告)日：1986-01-31
申请号：JP14238684
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KOWASE YASUAKI , ICHIKAWA TAKAYOSHI , TAKAGI TATSUTOSHI , AKAMATSU YOSHINORI , ISHIKAWA MAKOTO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0248
摘要： PURPOSE:To disperse energy of high voltage surge applied and assure certain protective operation through enhancement of rigidity of protection element by guiding a high voltage surge to the largest conductive region in the three conductive regions to form a bipolar transistor. CONSTITUTION:The side of collectors 62, 63 of the pnp bipolar transistor Q1 and the npn bipolar transistor Q2 is respectively connected to the side of external input pad Pi. Therefore, the base and emitter of the pnp bipolar transistor Q1 are connected to the positive power source Vcc, while the base and emitter of the npn bipolar transistor Q2 to the ground potential. In this case, if any type of positive and negative high voltage surges is not applied to the input terminal pad Pi, the base to emitter voltage becomes almost zero at each transistor Q1, Q2. Therefore, these transistors maintain in the OFF (non-conductive) state. Accordingly, these can operate as the protection elements for any of positive and negative high voltage surges.
摘要翻译：目的：为了分散施加的高压浪涌能量，通过将高压浪涌引导到三个导电区域中的最大导电区域，通过增强保护元件的刚性来确保一定的保护操作，以形成双极晶体管。构成：pnp双极晶体管Q1和npn双极晶体管Q2的集电极62,63的一侧分别连接到外部输入焊盘Pi的一侧。因此，pnp双极晶体管Q1的基极和发射极连接到正电源Vcc，而npn双极晶体管Q2的基极和发射极接地电位。在这种情况下，如果没有对输入端子焊盘Pi施加任何类型的正和负高压浪涌，则在每个晶体管Q1，Q2处的基极对发射极电压变为几乎为零。因此，这些晶体管保持OFF（非导通）状态。因此，这些可以作为用于任何正和负高压浪涌的保护元件。

8. 发明专利

JPS6143463A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6143463A
公开(公告)日：1986-03-03
申请号：JP16499184
申请日：1984-08-08
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： INABA TORU , KONDO SHIZUO , TAKAGI TATSUTOSHI , KOWASE YASUAKI , ICHIKAWA TAKAYOSHI
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8234 , H01L27/088 , H01L29/40
CPC分类号： H01L21/8221
摘要： PURPOSE:To contrive to stabilize the operation of the circuit of a semiconductor device by a method wherein a metal layer is made to interpose in the insulating films and the metal film is earthed to shield. CONSTITUTION:SiO2 is deposited on the whole surface of the substrate by a vapor-phase chemical deposit CVD method and a thick SiO2 film 6 is formed. An Al film 7 to be used for shielding is formed on this film 6 by performing an evaporation of Al and so forth. Then, SiO2 is deposited on the whole surface by a CVD method in such a way as to bury the Al film 7 in the SiO2 and an a-Si film 10 is formed on an SiO2 film 9 deposited by decomposing SiH4 according to a glow discharge. Then, Mo electrodes are formed on both end parts of the film 10, SiO2 is deposited, a gate insulating film 12 is provided on the film 10, an etching is performed on parts of the film 9 to open through holes 13 and 14, and the Al electrodes 15a, 15b and 15c of the element on the upper stage, which are connected to the Al electrodes 5a and 5b of the element on the lower stage, are provided. Moreover, the electrode 15c is connected to the film 7 for shielding and the film 7 is earthed as the terminal for shielding.
摘要翻译：目的：通过以下方法来稳定半导体器件的电路的工作，其中使金属层插入绝缘膜并且金属膜接地以进行屏蔽。构成：通过气相化学沉积CVD法在基板的整个表面上沉积SiO 2，形成厚的SiO 2膜6。通过Al的蒸发等在该膜6上形成用于屏蔽的Al膜7。然后，通过CVD法将SiO 2沉积在整个表面上，以将Al膜7埋入SiO 2中，并且通过根据辉光放电来分解SiH 4沉积的SiO 2膜上形成a-Si膜10 。然后，在膜10的两端形成Mo电极，淀积SiO 2，在膜10上设置栅极绝缘膜12，对膜9的一部分进行蚀刻，开通通孔13,14。提供与上级元件的Al电极5a和5b连接的上级元件的Al电极15a，15b和15c。此外，电极15c连接到用于屏蔽的膜7，并且膜7接地作为屏蔽端子。

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