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1. 发明专利

JPH0115142B2 失效
公开(公告)号：JPH0115142B2
公开(公告)日：1989-03-15
申请号：JP22618182
申请日：1982-12-24
申请人： HITACHI LTD
发明人： OGURA SADAO , INABA TOORU , TAKAGI TATSUTOSHI
IPC分类号： H01L23/522 , H01L21/768

2. 发明专利

JPS60224229A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60224229A
公开(公告)日：1985-11-08
申请号：JP7856684
申请日：1984-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TEZUKA IZUMI , SAKURAI SHIYUUICHI , INABA TOORU , MATSUMOTO MASATO
IPC分类号： H01L23/522 , H01L21/31 , H01L21/312 , H01L21/768
摘要： PURPOSE:To stop decreasing of moisture resistance due to the influence of phosphorus to the first wiring layer without altering the present process by forming the first layer wiring of wirings through an inorganic insulating film containing no phosphorus on an inorganic insulating film which contains phosphorus oxide glass layer on the surface. CONSTITUTION:A glass (PSG) film 7 which contains high density phosphorus oxide is formed on the surface of a silicon oxide 2 for coating the surface of a semiconductor element formed on the other portion of the surface of a substrate 1. An inorganic insulating film 8 which does not contains phosphorus, formed on the film 7 is made, for example, of glass (SOG) by coating and silicon oxide by CVD not doped with nitride or phosphorus due to plasma discharging. The first layer wirings made of aluminum are formed as an electrode contacted with low resistance with the element, and partly extended on the film 8.

3. 发明专利

JPS6058651A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6058651A
公开(公告)日：1985-04-04
申请号：JP16661283
申请日：1983-09-12
申请人： HITACHI LTD
发明人： KOWASE YASUAKI , INABA TOORU , KONDOU SHIZUO , MINAMIMURA EIJI , HIRASHIMA TOSHINORI
IPC分类号： H01L27/00 , H01L21/822 , H01L27/04 , H01L27/06 , H01L29/30 , H01L29/78 , H01L29/786
摘要： PURPOSE:To improve the integration degree by construction of the title device in three dimensions by a method wherein semiconductor elements such as a transistor are formed in the surface layer part of an Si substrate, an amorphous Si layer being grown thereon, and an MOSFET consisting of an insulation gate electrode and source and drain electrodes sandwiching it being then provided therein. CONSTITUTION:A P type base region 2 is diffusion-formed in the surface layer part of the N type Si substrate 1, an N type emitter region 3 being then provided therein, and Al electrode wirings 5 contacting the regions 2 and 3, respectively, being then adhered after adhesion of an SiO2 film 4 over the entire surface and then by boring apertures, which are then covered with an SiO2 film 6 into the transistor. Next, the amorphous Si layer 7 is deposited on the film 6, P type regions 8 serving as the source and drain being diffusion-formed in its surface layer, and an Al gate electrode 11 being then mounted between the regions 8 after adhesion of an SiO2 film 9 over the entire surface. Besides, apertures are bored in the film 9, and the regions 8 are provided with Al electrodes 10, respectively, resulting in the formation of an FET. Thus, the Si layer 7 is made to function as a variable resistance layer, and the transistor is controlled by variation in voltages impressed on the electrodes 11.

4. 发明专利

JPS59208851A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS59208851A
公开(公告)日：1984-11-27
申请号：JP8265483
申请日：1983-05-13
申请人： Hitachi Ltd
发明人： INABA TOORU
IPC分类号： H01L27/08 , H01L21/02 , H01L21/265 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76297
摘要： PURPOSE:To improve the density of integration by forming an insulating film on a side surface section isolating elements through the implantation of impurity ions and obtaining an isolation in an extremely narrow region. CONSTITUTION:A semiconductor substrate 1 is prepared, and an insulating film 13 consisting of SiO2 or Si3N4 obtained by combining O2 or N2 and Si is formed in predetermined depth by implanting impurity ions such as O2 or N2 to the whole surface on one main surface of the substrate and controlling the energy of the implantation. An impurity implantation control mask 2 is formed on the surface of a semiconductor substrate 1b. The impurity implantation control mask has an inclined section in its side surface, and impurity ions are implanted through the mask 2 to form insulating films 3a, 3b for isolating elements surrounding the bottoms and side surfaces of one semiconductor regions. Si gates 6, n type sources-drains 10 and p type sources-drains 8 are each shaped to the surfaces of each region in a self-alignment manner through selective diffusion.
摘要翻译：目的：通过在杂质离子的注入和在极窄的区域中获得隔离来在侧表面部隔离元件上形成绝缘膜来提高积分密度。构成：制备半导体衬底1，并且通过将O 2或N 2与Si结合而获得的由SiO 2或Si 3 N 4组成的绝缘膜13通过在诸如O 2或N 2之类的杂质离子注入到一个主表面上的整个表面上而以预定的深度形成底物并控制植入能量。在半导体衬底1b的表面上形成杂质注入控制掩模2。杂质注入控制掩模在其侧表面具有倾斜部分，并且通过掩模2注入杂质离子，以形成用于隔离围绕一个半导体区域的底部和侧表面的元件的绝缘膜3a，3b。 Si栅极6，n +型源极 - 漏极10和p +型源极 - 漏极8分别通过选择性扩散以自对准方式成形为每个区域的表面。

5. 发明专利

JPS59107558A Semiconductor device containing capacitance element 失效
标题翻译：包含电容元件的半导体器件
公开(公告)号：JPS59107558A
公开(公告)日：1984-06-21
申请号：JP21691782
申请日：1982-12-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： INABA TOORU , TAKAGI TATSUHAYA , KOWASE YASUAKI , MATSUMOTO MASATO
IPC分类号： H01L27/04 , H01L21/265 , H01L21/822
CPC分类号： H01L21/265
摘要： PURPOSE:To increase capacitance per unit area, and to improve the degree of freedom on the formation of capacitance by using upper and lower semiconductor single crystal layers isolated by an insulating film formed in a Si substrate as electrode lead out sections. CONSTITUTION:An n epitaxial layer 3 on the p type Si single crystal substrate 1 into which an n layer is buried is insulated and isolated 4. O2 ions are implanted into an isolated region, the layer 3 is annealed, and a SiO2 film 5 is formed in predetermined depth to isolate the layer 3 into single crystal layers 3a, 3b. One part of the layer 3a is removed through etching up to the layer 3b to form a recessed section 6, windows are bored to a SiO2 film 7 formed to the surface, n layers 8a, 8b are each formed to the layers 3a, 3b, and Al electrodes (A), (B) are attached. An extremely thin film is obtained by the quantity of ions implanted as the insulating film 5, and capacitance per the unit area can be increased in the film 5. The degree of freedom on the formation of capacitance is improved because the depth of the insulating film 5 can be controlled with high accuracy by changing the energy of implantation and shapes are also selected arbitrarily.
摘要翻译：目的：通过使用通过在Si衬底中形成的绝缘膜隔离的上半导体单晶层和下半导体单晶层作为电极引出部，来增加每单位面积的电容，并提高形成电容的自由度。构成：在掩埋有n +层的p型Si单晶衬底1上的n外延层3被绝缘和隔离4.将O 2离子注入到隔离区域中，层3退火，并且将SiO 2 以预定深度形成膜5，以将层3隔离成单晶层3a，3b。层3a的一部分通过蚀刻被去除到层3b以形成凹陷部分6，窗口被钻孔到形成于表面的SiO 2膜7，n +层8a，8b各自形成于层3a ，3b和Al电极（A），（B）。通过作为绝缘膜5注入的离子的量获得极薄的膜，并且可以在膜5中增加单位面积的电容。由于绝缘膜的深度，形成电容的自由度得到改善通过改变植入能量可以高精度地控制5，也可任意选择形状。

6. 发明专利

JPS5843911B2 失效
公开(公告)号：JPS5843911B2
公开(公告)日：1983-09-29
申请号：JP7833573
申请日：1973-07-13
申请人： HITACHI LTD
发明人： INABA TOORU
IPC分类号： H01L29/80 , H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/73 , H01L29/808

7. 发明专利

JPS57128073A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57128073A
公开(公告)日：1982-08-09
申请号：JP20533081
申请日：1981-12-21
申请人： HITACHI LTD
发明人： INABA TOORU
IPC分类号： H01L29/80 , H01L21/8222 , H01L21/8248 , H01L27/06
摘要： PURPOSE:To easily perform the control of the channel width between gates for the subject device by a method wherein, when a J-FET and a bipolar transistor are provided on the same semiconductor substrate, the gate region of the FET is divided into a plurality of parts, and shallow source regions are provided in a contact state among the divided parts. CONSTITUTION:N type impurities are separately on the surface of a P type Si substrate 11, an N type layer 33 is epitaxially grown on the whole surface including the above, and at the same time, the impurities deposited previously are diffused, and buried regions 32a and 32b are formed. Then, using the P type region 34 which is penetrated to the substrate 11, the layer 33 is divided into two island type layers 33a and 33b, including regions 32a and 32b respectively, and the layer 33 is used for the J-FET and the layer 33b is used for the bipolar transistor 35c. Subsequently, P type gate regions 35a-35c are formed by diffusion leaving an interval among them, and shallow N type source regions 36a and 36b are provided among the regions 35a-35c. Also, a P type base region is formed by diffusion in the layer 33a, and inside of which an N type emitter region is provided.

8. 发明专利

JPS54121673A INSULATOR COATING MATERIAL AND SEMICONDUCTOR DEVICE USING THE SAID MATERIAL 失效
公开(公告)号：JPS54121673A
公开(公告)日：1979-09-20
申请号：JP2868078
申请日：1978-03-15
申请人： HITACHI LTD
发明人： INABA TOORU
IPC分类号： H01L21/52 , H01L21/58
摘要： PURPOSE:To prevent the insulator coating from being thinned at the periphery of the tub by putting the insulator solid state piece of glass, alumina or the like into the paste composed of the epoxy resin or the polyimide resin to secure the thixotropic property. CONSTITUTION:The epoxy resin of about 20 wt% and the slender needle type pieces of about 80 wt% glass powder are mixed into the nonvolatile organic solvent to obtain the insulator coating agent. At the same time, the polyimide resin of 5-50 wt% and the alumina powder of 50-90 wt% are mixed also into the nonvolatile organic solvent agent and then mixed up well at the normal temperature to obtain the paste featuring the thixotropic property. This paste is then dropped down to the central region of tub 1 via the potting method to form insulator coating layer 7, and the air is sprayed through nozzle 8 to the center of layer 7 to obtain coating material layer 9 which is thin at the center and thick at the circumference area. Semiconductor pellet 3 is adhered onto layer 9. In this case, the short circuit can be avoided between tub 1 and the wire hung down owing to the thick circumference of layer 9.

9. 发明专利

JPS5285474A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5285474A
公开(公告)日：1977-07-15
申请号：JP152776
申请日：1976-01-09
申请人： HITACHI LTD
发明人： INABA TOORU
IPC分类号： H01L21/768 , H01L21/31 , H01L21/312 , H01L23/522
摘要： PURPOSE:To achieve the improvement in moisture resistance by completely covering the surface of a semiconductor device.

10. 发明专利

JPS5230185A PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5230185A
公开(公告)日：1977-03-07
申请号：JP10591675
申请日：1975-09-03
申请人： HITACHI LTD
发明人： INABA TOORU
IPC分类号： H01L27/00 , H01L21/02 , H01L21/265 , H01L21/76 , H01L21/762 , H01L27/12
摘要： PURPOSE:To provide a semiconductor integrated circuit device having a high pressure resistance, wherein the isolation zone and parasitics effects are minimized by forming the insulation layer through ion implanting method and by using the anisotropic etching.

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