专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

NO332862B1 未知
公开(公告)号：NO332862B1
公开(公告)日：2013-01-28
申请号：NO20101767
申请日：2010-12-17
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , WATANABE KAZUO , HOTTA MASAO , HONGO TOYOHIKO , YAMAWAKI TAIZO , KASAHARA MASUMI , TAKIKAWA KUMIKO
IPC分类号： H04B1/40 , H03D7/14 , H03F1/32 , H03F3/34 , H03G3/30 , H03M1/06 , H04B1/30 , H04B1/38 , H04B1/3822 , H04B7/00 , H04L27/38 , H04M20060101 , H04M1/00 , H04Q7/32
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers (105, 115, 116, 119, 120, 141) to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers (105, 115, 116) each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider (119, 120, 141) having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier (108) for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit (110) for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

2. 发明专利

DE19527347B4 未知
公开(公告)号：DE19527347B4
公开(公告)日：2007-10-11
申请号：DE19527347
申请日：1995-07-26
申请人： HITACHI LTD , HITACHI AUTOMOTIVE ENG
发明人： KATAYAMA HIROSHI , KAYANO MITSUO , WATABE MITSURU , ISHII JUNICHI , ICHIHASHI TETSUYA , SASAKI SHOJI , TANAKA SATOSHI
IPC分类号： F02D45/00 , G05B19/042 , F02D41/24 , F02D41/26 , F02D43/00 , F02P5/15 , F02P7/077 , G05B15/02 , G06F1/04 , G06F15/78
摘要： A control processor has an output pattern generating circuit operating in cooperation with a free running timer, and a virtual OCR program for virtually realizing a large number of timer outputs by use of the output pattern generating circuit. Because more timer outputs than the actually incorporated timers are handled, the function of timer outputs is implemented with a higher degree of freedom and in a wider range of applications. For its enhanced function and availability, the control processor costs less.

3. 发明专利

DE69530645T2 未知
公开(公告)号：DE69530645T2
公开(公告)日：2004-03-11
申请号：DE69530645
申请日：1995-08-28
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , OKAMOTO TATSUTO , KITAYAMA TARO , YAMANE MASAO
IPC分类号： H01P1/15 , H03K17/06 , H03K17/16 , H03K17/687 , H03K17/693
摘要： In an SPDT switch consisting of a plurality of FETs, the FET (FET 2) on the receiver side through which a received signal passes and the shunt FET (FET 4) on the transmitter side are each formed of series-connected FETs, and a capacitor is connected between the first gate and the source and between the second gate and the drain. An inductance is connected in parallel with a series connection of FETs. This easily realises a high frequency switch having a low voltage and a low distortion characteristic. The 1 dB compression level, an index of input-output characteristic, can be improved by more than 5 dB over the conventional SPDT switch at an input level.

4. 发明专利

NO20101767L 未知
公开(公告)号：NO20101767L
公开(公告)日：2001-05-16
申请号：NO20101767
申请日：2010-12-17
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , WATANABE KAZUO , HOTTA MASAO , HONGO TOYOHIKO , YAMAWAKI TAIZO , KASAHARA MASUMI , TAKIKAWA KUMIKO
IPC分类号： H04B1/40 , H04M1/00 , H04B1/30 , H04B1/38 , H04B1/3822 , H04B7/00 , H04L27/38 , H04M20060101 , H04M1/30 , H04M1/32 , H04M1/40 , H04Q7/32
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers (105, 115, 116, 119, 120, 141) to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers (105, 115, 116) each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider (119, 120, 141) having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier (108) for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit (110) for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

5. 发明专利

NO20005772L 未知
公开(公告)号：NO20005772L
公开(公告)日：2001-05-16
申请号：NO20005772
申请日：2000-11-14
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , WATANABE KAZUO , HOTTA MASAO , HONGO TOYOHIKO , YAMAWAKI TAIZO , KASAHARA MASUMI , TAKIKAWA KUMIKO
IPC分类号： H04B1/40 , H04B1/30 , H04B1/38 , H04B1/3822 , H04B7/00 , H04L27/38 , H04M20060101 , H04M1/00 , H04Q7/32
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers (105, 115, 116, 119, 120, 141) to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers (105, 115, 116) each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider (119, 120, 141) having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier (108) for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit (110) for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

6. 发明专利

DE60041784D1 未知
公开(公告)号：DE60041784D1
公开(公告)日：2009-04-23
申请号：DE60041784
申请日：2000-01-11
申请人： TTP COMMUNICATIONS LTD , HITACHI LTD
发明人： YAMAWAKI TAIZO , TANAKA SATOSHI , KOKUBO MASARU , WATANABE KAZUO , KASAHARA MASUMI , HORI KAZUAKI , HILDERSLEY JULIAN
IPC分类号： H04B1/04 , H03C3/09 , H03D7/00 , H03D7/16 , H03L7/18 , H03L7/185 , H03L7/23 , H04B1/38 , H04L25/03 , H04L27/12
摘要： A transmitter in which the problem of unwanted spurious signals due to harmonics of the output signal from a frequency synthesizer and due to mixture of harmonics of the output signal from a crystal oscillator into a VCO and which facilitates the design of circuits and mounting boards, and a terminal using the transmitter are disclosed. In the transmitter, the relationship between the output frequency of a frequency converting circuit (5) comprising a PLL and the output frequencies of frequency synthesizers (1, 2) is stored. By controlling the output frequencies of the frequency synthesizers inputted to the frequency converting circuit (5) according to the relationship, the unwanted spurious signal is suppressed. Thus, even if an unwanted spurious signal is included in the output of the transmitter because of the crosstalk between circuits and boards, the spurious signal can be suppressed, thereby shortening the time to re-design circuits and boards and reducing the r e-designing cost.

7. 发明专利

GB2382242B Direct-conversion transmitting circuit and integrated transmitting/receiving circuit 未知
公开(公告)号：GB2382242B
公开(公告)日：2005-08-03
申请号：GB0127422
申请日：2001-11-15
申请人： HITACHI LTD , HITACHI DEVICE ENG , TTP COMMUNICATIONS LTD
发明人： TANAKA SATOSHI , TANABE MASAMICHI , OKUMA YASUYUKI , YAMAWAKI TAIZO , YAHAGI KOICHI , MATSUI HIROAKI , HENSHAW ROBERT ASTLE
IPC分类号： H04L27/36 , H03C3/40 , H03D7/14 , H04B1/04 , H04B1/40 , H03C3/02
摘要： A three band GSM (800MHz, 1800MHz, 1900MHz) transmitter/receiver comprises direct conversion mixers and one RF PLL synthesiser with a VCO. In order to reduce DC-offset, to reduce the number of parts and to achieve noise reduction in the receiving band, low-pass filters (130 and 131) are provided at IQ input sections of a modulator (106) that converts IQ signals into RF signals. In comparison with a conventional transmitter using an offset PLL, an external VCO in addition to an RF integrated circuit, a power amplifier, and a front end are used. The circuit does not require an expensive and external high frequency filter such as a surface acoustic wave (SAW) filter or the like.

8. 发明专利

NO20005772A 未知
公开(公告)号：NO20005772A
公开(公告)日：2001-05-16
申请号：NO20005772
申请日：2000-11-14
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , WATANABE KAZUO , HOTTA MASAO , HONGO TOYOHIKO , YAMAWAKI TAIZO , KASAHARA MASUMI , TAKIKAWA KUMIKO
IPC分类号： H04B1/40 , H04B1/30 , H04B1/38 , H04B1/3822 , H04B7/00 , H04L27/38 , H04M20060101 , H04M1/00 , H04Q7/32
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16

9. 发明专利

DE60309989D1 未知
公开(公告)号：DE60309989D1
公开(公告)日：2007-01-11
申请号：DE60309989
申请日：2003-09-05
申请人： HITACHI LTD
发明人： SUZUKI MAY , TANAKA SATOSHI , YAMAWAKI TAIZO , TANOUE TOMONORI
IPC分类号： H03F1/02 , H03F3/24
摘要： The invention provides an amplifier circuit for wireless communication apparatus. In this circuit, a linear system and an EER system are used in combination such that the EER system can also be used in a cellular phone with a wide output dynamic range. In the EER mode, linear control of an amplifier becomes difficult in the low output range. Thus, the use of the EER system is limited to the high output range, and the linear system is used in the low output range. The power efficiency is improved while the requirements of linearity are satisfied by this structure. An effective circuit structure is proposed for a switching control system. The amplifier circuit system comprises a quadrature modulator (403), an AGC amplifier (404), a power amplifier (408), and an amplitude modulation circuit (405), and is designed such that the amplifier circuit is operating in an EER mode at high output power and in a linear, fixed supply mode at low output power.

10. 发明专利

DE69922587D1 未知
公开(公告)号：DE69922587D1
公开(公告)日：2005-01-20
申请号：DE69922587
申请日：1999-06-01
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , ISHIFUJI TOMOAKI , NAGAI KENJI , FURUKAWA KATSUHIRO
IPC分类号： G06K17/00 , G06K7/00 , H04B5/02 , H04L12/28 , H04L25/49 , G06K19/07

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式