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1. 发明授权

CN103181120B 存储在快和慢存储器中的统计计数器失效
公开(公告)号：CN103181120B
公开(公告)日：2016-04-20
申请号：CN201180046118.2
申请日：2011-09-19
申请人：瑞典爱立信有限公司
发明人：陈振宇 , B.阿利恩 , R.哈萨维 , R.J.罗扎里奥 , T.巴索
IPC分类号： H04L12/26 , H04L12/24 , H03K21/16
CPC分类号： H03K21/38 , H03K21/16
摘要：一种在存储器控制器中执行的用于保持分段式计数器的方法，该分段式计数器分在主存储器和辅助存储器中，主存储器更快。需要递增分段式计数器中的一个的事件发生并且存储器控制器通过递增主存储器中的对应初级部分来进行响应。每次初级部分翻转时，存储器控制器确定应该更新次级部分。而且，存储器控制器周期性地确定应该机遇式更新分段式计数器的次级部分。机遇式更新基于概率函数和随机数。次级部分至少包含分段式计数器的未包括在初级部分中的所有比特并且存储在辅助存储器中。每次发生对次级部分的更新时，必须更新分段式计数器的次级部分和初级部分两者。

2. 发明公开

CN103181120A 存储在快和慢存储器中的统计计数器失效
公开(公告)号：CN103181120A
公开(公告)日：2013-06-26
申请号：CN201180046118.2
申请日：2011-09-19
申请人：瑞典爱立信有限公司
发明人：陈振宇 , B.阿利恩 , R.哈萨维 , R.J.罗扎里奥 , T.巴索
IPC分类号： H04L12/26 , H04L12/24 , H03K21/16
CPC分类号： H03K21/38 , H03K21/16
摘要：一种在存储器控制器中执行的用于保持分段式计数器的方法，该分段式计数器分在主存储器和辅助存储器中，主存储器更快。需要递增分段式计数器中的一个的事件发生并且存储器控制器通过递增主存储器中的对应初级部分来进行响应。每次初级部分翻转时，存储器控制器确定应该更新次级部分。而且，存储器控制器周期性地确定应该机遇式更新分段式计数器的次级部分。机遇式更新基于概率函数和随机数。次级部分至少包含分段式计数器的未包括在初级部分中的所有比特并且存储在辅助存储器中。每次发生对次级部分的更新时，必须更新分段式计数器的次级部分和初级部分两者。

3. 发明授权

EP0370924B1 Compteur d'impulsions d'horloge à fréquence élevée 失效
标题翻译：高频时钟脉冲计数器。
公开(公告)号：EP0370924B1
公开(公告)日：1994-03-16
申请号：EP89420453.6
申请日：1989-11-20
申请人： SEXTANT AVIONIQUE S.A.
发明人： Payen, Hubert , Pain, Bernard
IPC分类号： H03K21/12
CPC分类号： H03K21/12 , H03K21/16 , H03K23/50

4. 发明授权

US08107912B2 Mobile communication apparatus 有权
标题翻译：移动通信装置
公开(公告)号：US08107912B2
公开(公告)日：2012-01-31
申请号：US12975488
申请日：2010-12-22
申请人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B1/06 , H04B7/00 , H04B1/10
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

5. 发明申请

US20080182538A1 MOBILE COMMUNICATION APPARATUS 有权
标题翻译：手机通讯设备
公开(公告)号：US20080182538A1
公开(公告)日：2008-07-31
申请号：US12056576
申请日：2008-03-27
申请人： Satoshi TANAKA , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi TANAKA , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B1/06 , H04B1/10
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

6. 发明授权

US07092479B1 Ripple counter circuits in integrated circuit devices having fast terminal count capability and methods of operating the same 有权
标题翻译：具有快速终端计数能力的集成电路设备中的纹波计数器电路及其操作方法
公开(公告)号：US07092479B1
公开(公告)日：2006-08-15
申请号：US10931699
申请日：2004-09-01
申请人： David Reid , Timothy Gillespie
发明人： David Reid , Timothy Gillespie
IPC分类号： G06F3/00
CPC分类号： H03K21/16
摘要： Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ripple counter circuit has been reached. Related methods are also disclosed.
摘要翻译：集成电路设备中的纹波计数器电路可以具有快速的终端计数能力。终端计数电路可以被配置为使用纹波计数器电路的终端状态已经到达的指示来屏蔽由纹波计数器电路产生的选择的不稳定计数器位。还公开了相关方法。

7. 发明申请

WO2012038882A1 STATISTICS COUNTER STORED IN FAST AND SLOW MEMORIES 审中-公开
标题翻译：统计数据库存储在快速和慢速记忆中
公开(公告)号：WO2012038882A1
公开(公告)日：2012-03-29
申请号：PCT/IB2011/054101
申请日：2011-09-19
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , CHEN, Edmund G. , ALLEYNE, Brian , HATHAWAY, Robert , ROZARIO, Ranjit J. , BASSO, Todd
发明人： CHEN, Edmund G. , ALLEYNE, Brian , HATHAWAY, Robert , ROZARIO, Ranjit J. , BASSO, Todd
IPC分类号： H04L12/26 , H04L12/24 , H03K21/16
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定要更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

8. 发明申请

WO2012038882A9 STATISTICS COUNTERS STORED IN FAST AND SLOW MEMORIES 审中-公开
标题翻译：统计数据库存储在快速和缓慢的记忆
公开(公告)号：WO2012038882A9
公开(公告)日：2013-11-21
申请号：PCT/IB2011054101
申请日：2011-09-19
申请人： ERICSSON TELEFON AB L M , CHEN EDMUND G , ALLEYNE BRIAN , HATHAWAY ROBERT , ROZARIO RANJIT J , BASSO TODD
发明人： CHEN EDMUND G , ALLEYNE BRIAN , HATHAWAY ROBERT , ROZARIO RANJIT J , BASSO TODD
IPC分类号： H04L12/26 , H03K21/16 , H04L12/24
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定要更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

9. 发明授权

US08406370B2 Counter circuit and solid-state imaging device 有权
标题翻译：计数电路和固态成像装置
公开(公告)号：US08406370B2
公开(公告)日：2013-03-26
申请号：US13179009
申请日：2011-07-08
申请人： Kazuki Hizu
发明人： Kazuki Hizu
IPC分类号： H03K23/00
CPC分类号： H03K21/026 , H03K21/16
摘要： According to one embodiment, S (S is an integer equal to or larger than two) number of sub counters each count S number of clocks of different frequencies, and a clock switching unit is provided for each sub counter and starts a counting operation of a sub counter of a next stage after finishing a counting operation in a sub counter of a local stage.
摘要翻译：根据一个实施例，S（S是等于或大于2的整数）个子计数器的数量，每个计数不同频率的时钟数，并且为每个子计数器提供时钟切换单元，并开始计数操作在本地级的子计数器中完成计数操作之后的下一级的副计数器。

10. 发明授权

US07366489B2 Mobile communication apparatus 有权
标题翻译：移动通信装置
公开(公告)号：US07366489B2
公开(公告)日：2008-04-29
申请号：US10742813
申请日：2003-12-23
申请人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
发明人： Satoshi Tanaka , Kazuo Watanabe , Masao Hotta , Toyohiko Hongo , Taizo Yamawaki , Masumi Kasahara , Kumiko Takikawa
IPC分类号： H04B1/06 , H04B1/10
CPC分类号： H04B1/30 , H03D2200/0047 , H03K21/16
摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
摘要翻译：适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除消除。

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