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1. 发明专利

JPH08250683A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250683A
公开(公告)日：1996-09-27
申请号：JP6407796
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve an adhesion property between a base insulating film and a wiring, and improve processing accuracy of the wiring and a transition metal film underlying the wiring by forming a second metal film formed by a CVD process on a first metal film formed by a sputtering process. CONSTITUTION: This device comprises a plurality of wirings 55 consisting of an insulating film (base insulating film) 53 formed on a principal surface of a semiconductor substrate 20 and a metal film (transition metal film) 54 formed on the base insulating film 53. The transition metal film 54 includes a first metal film formed by a sputtering process and a second metal film formed by a CVD process. The second metal film is formed on the first metal film. The first metal film has its thickness thinner than that of the second metal film. The first and second metal films comprise the same material. Hereby, the transition metal film 54 deposited by a sputtering process has a higher adhesion property with each of the base insulating film 53 and the wiring 55 so that an adhesion property between the base insulating film 53 and the wiring 55 can be improved.

2. 发明专利

JPH0846041A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0846041A
公开(公告)日：1996-02-16
申请号：JP18119194
申请日：1994-08-02
申请人： HITACHI LTD
发明人： SAITO TOSHIO , AKIMORI HIROYUKI
IPC分类号： H01L23/522 , H01L21/316 , H01L21/768
摘要： PURPOSE:To provide a highly reliable layer insulation film by providing an electric wiring layer formed on a semiconductor substrate, an SOG film formed thereon and an SOG film which is formed on a surface thereof and is thicker than the SOG film. CONSTITUTION:An item wherein an n-channel MOSFET is formed using a semiconductor substrate as a starting material is illustrated as a substrate 9 inclusively. An electric wiring layer 10 is formed in a surface of an insulation film 8 formed on the substrate 9. An SOG film 13 formed on the electric wiring layer 10 and an SOG film 14 which is formed on a surface of the SOG film 13 and is thicker than the SOG film 13 are provided. The double layer structure SOG films 13, 14 are applied as a layer insulation film of the electric wiring layer 10. Therefore, the SOG film 13 of a lower layer buried in a recessed part, etc., of the electric wiring layer 10 becomes thick enough to attain satisfactory effect of thermal treatment and highly reliable SOG films 13, 14 can be provided.

3. 发明专利

JPH06268074A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06268074A
公开(公告)日：1994-09-22
申请号：JP5553393
申请日：1993-03-16
申请人： HITACHI LTD
发明人： SAITO TOSHIO , AKIMORI HIROYUKI
IPC分类号： H01L23/522 , H01L21/768 , H01L21/90
摘要： PURPOSE:To provide a semiconductor device having improved reliability and a manufacturing technique therefor by preventing the deformation of wiring patterns during heat treatment. CONSTITUTION:The title semiconductor device consists of a lower wiring pattern 2 formed on an insulating base layer 1; a first layer insulating film 3; through holes 3a formed in the first layer insulating film 3; an upper wiring pattern 4 which is formed in a specified shape on the first layer insulating film 3, and which has a connection 4b connected with the lower wiring pattern 2 through the through holes 3a; and a second layer insulating film 5. The second layer insulating film 5 is constituted of three layers: lower plasma CVD film 5a, intermediate layer SOG film 5b and upper plasma CVD film 5c. The thickness H of the lower plasma CVD film 5a above the connection 4a of the upper wiring pattern 4 within the through hole 3a, is controlled to meet the condition: H>=0.15mum.

4. 发明专利

JPH0352234A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0352234A
公开(公告)日：1991-03-06
申请号：JP18849989
申请日：1989-07-20
申请人： HITACHI LTD
发明人： OWADA NOBUO , SASABE SHUNJI , FUJIWARA TAKESHI , AKIMORI HIROYUKI
IPC分类号： H01L21/3205 , H01L21/768
摘要： PURPOSE:To achieve perfect flattening of steps in a wiring Iayer at a high throughput by forming an interlayer insulating film by a step for depositing a CVD insulating film and an etch-back step. CONSTITUTION:An interlayer insulating film is formed by a step for depositing a CVD insulating film 3 and an etch-back step. In the CVD insulating film depositing step, the formation of the CVD insulating film 3 on the side wall part of a pattern on the step side on a semiconductor substrate 2 becomes substantially zero. In the etch-back step, a sputter etching technology and isotropic etching technology are combined. Thus, the interlayer insulating film can be made flat perfectly. Even if wiring layers are stacked, the flatness of the surface of the wiring Iayer is maintained. The reliability of a connecting hole which is conducted through the wiring layers can be improved.

5. 发明专利

JPH11328255A TIME SEQUENTIAL DATA FLUCTUATION MONITORING DEVICE AND STORAGE MEDIUM STORING PROGRAM RELATING TO THE DEVICE 失效
公开(公告)号：JPH11328255A
公开(公告)日：1999-11-30
申请号：JP13149098
申请日：1998-05-14
申请人： HITACHI LTD
发明人： MAKI HIDEYUKI , MORITA TOYOHISA , MAEDA AKIRA , AKIMORI HIROYUKI , OGAWA MIHOKO
IPC分类号： G06Q50/04 , G06Q50/00 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To automatically monitor the large amount of time sequential data of many kinds by comparing an object time sequence for which object values are arranged corresponding to the generation time and a derivative time sequence generated based on it and judging the change of the object time sequence. SOLUTION: A data base 102 holds the object value (the measured value of a working dimension for instance) and an attribute value (the time of performing working for instance) accompanying the object value as a set. By a selection means 103, the set 110 of attribute sets is generated. The object values are summed up by a sum-up means 104 and the set 111 of the summed-up attribute sets is generated for the respective sets 110 of the attribute sets. A derivative time sequence generation means 105 performs a prescribed arithmetic operation to the object time sequence for which the summed-up attribute sets are arranged in the order of the generation time and generates the derivative time sequence 112. By a change judgement means 106, the object time sequence and the derivative time sequence are compared and the change is judged. A reporting means 107 reports the result of change judgement to a user 109.

6. 发明专利

JPH02106968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FORMING METHOD THEREOF 失效
公开(公告)号：JPH02106968A
公开(公告)日：1990-04-19
申请号：JP26103588
申请日：1988-10-17
申请人： HITACHI LTD
发明人： OWADA NOBUO , AKIMORI HIROYUKI , NITTA TAKEHISA , KOBAYASHI TORU , SASABE SHUNJI , KAWAJI MOTONORI , KASAHARA OSAMU
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/118
摘要： PURPOSE:To improve the mounting efficiency of a circuit while reducing memory capacitance by making the wiring pitch of a third layer wiring substantially the same as or smaller than that of a first layer wiring. CONSTITUTION:In a logic LSI having multilayer interconnection structure formed by an automatic wiring arrangement system, first layer signal wirings 38 having multilayer interconnection structure and third layer signal wirings 44 are extended in the X direction and second layer signal wirings 41 in the Y direction respectively, and the wiring pitch P3 of the third layer signal wirings 44 is made substantially the same as or smaller than that P1 of the first layer signal wirings 38. According to the constitution, the number of the signal wirings of the third layer signal wirings 44 is increased, and the number of the signal wirings of the first layer signal wirings 38, the third layer signal wirings 44 and the second layer signal wirings 41 can be equalized, thus improving the degree of freedom of the arrangement of the signal wirings in the automatic wiring arrangement system, then enhancing the mounting efficiency of a logic circuit.

7. 发明专利

JPS63122152A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63122152A
公开(公告)日：1988-05-26
申请号：JP26752686
申请日：1986-11-12
申请人： HITACHI LTD
发明人： AKIMORI HIROYUKI , HORIUCHI MITSUAKI , WATAOKA MASATOSHI
IPC分类号： H01L21/3205
摘要： PURPOSE:To enhance the step coverage of a wiring part at a connecting hole and, at the same time, to prevent a defect of poor conductivity between an upper-layer wiring part and an under-layer wiring part by a method wherein the connecting hole is shaped in such a way that more than one stepped parts is formed on the whole surface of the inner wall. CONSTITUTION:An interlayer insulating film 11, where, e.g., a comparatively thick SiO2 film is formed on a thin Si3N4 film, is formed so as to cover a wiring part 10; a second wiring part 12 (an upper-layer wiring part) composed of, e.g., an aluminum film is formed through a connecting hole 11a made on this interlayer insulating film 11. The whole surface of the inner wall of the connecting hole 11a is composed of parts 11b, 11c which are almost perpendicular to the surface of a semiconductor substrate 1 and of a part 11d which is almost parallel to the surface of the semiconductor substrate 1. For example, the inner wall having two steps is shaped. By this method, it is possible to reduce the aspect ratio of each stepped part even when this part is viewed from any direction. As a result, even when the wiring part 12 is extended in any direction with reference to the wiring part 10, it is possible to enhance the step coverage of the connecting hole 11a.

8. 发明专利

JPH08250681A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250681A
公开(公告)日：1996-09-27
申请号：JP6407496
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE: To flatten the surface of an interlayer insulating film by filling an interval between lower electrode layers with an interlayer insulating layer by making thicker the thickness of the interlayer insulating film than the specific amount of a distance between first electrodes of a memory cell where the first electrodes of the memory cell adjoin with a minimum interval. CONSTITUTION: This device comprises a plurality of word lines 27 that constitute a gate electrode 27 of a memory cell selecting MISFETQS, a first electrode 37 extending onto the word lines, and a second electrode 35 provided oppositely to the first electrode 37 through a dielectric 36. An interlayer insulating film 53 is provided between a second electrode 37 and a wiring 36. The first electrode 37 is independently of each memory cell M, and the second electrode 35 is formed commonly to a plurality of the memory cells. The interlayer insulating film 53 is constructed to be thicker than 1/2 of a distance between the first electrodes 37 where the first electrodes of the memory cell M adjoin with a minimum interval. Hereby, an interval between the lower layer electrode layers 35 is filled with the interlayer insulating film 53 to flatten the surface of the interlayer insulating film 53.

9. 发明专利

JPH08250601A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250601A
公开(公告)日：1996-09-27
申请号：JP6404696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve hot carrier withstand voltage by making virtually equal the dimensions in the direction of gate length of the semiconductor regions of low impurity concentration, which form the LDD structure of a first and a second MISFETs, respectively. CONSTITUTION: The n-channel MISFETs Qn of an input/output stage circuit and an internal circuit are composed of a gate insulating film 26, a gate electrode 27, a n-type semiconductor region 29, and a n--type semiconductor region 32, respectively. The side wall spacers 31 of these n-channel MISFETs Qn are virtually the same in size in the direction of gate length. The gate length of the n-channel MISFET Qn in the input/output stage circuit is made larger than that of the n-channel MISFET Qn in the internal circuit. Further, the n-type semiconductor regions 29 forming the LDD structure of the n-channel MISFETs are virtually the same in size in the direction of gate length. This improves hot carrier withstand voltage, and reduces threshold voltage drop with a lapse of time, which enables the improvement of electrical characteristics.

10. 发明专利

JPH08241969A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241969A
公开(公告)日：1996-09-17
申请号：JP6407696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the moisture-proof of a passivation film formed on an interconnection layer by a method wherein the film thickness of an insulating film formed on an aluminum interconnection is specified by using a CVD method in which tetraethoxysilane is used as a source gas. CONSTITUTION: A passivation film 56 is formed on interconnections 55 which are composed mainly of aluminum alloy films 55B. The passivation film 56 is constituted of a composite film in which each of a silicon oxide film 56A deposited by a C-CVD method by using tetraethoxysilane as a source gas and a silicon nitride film 56B deposited by a plasma CVD method have been laminated in order. The silicon oxide film 56A at the lower layer of the passivation film 56 is constituted at a film thickness at 1/2 or higher of the interval between the interconnections 55 in regions in which the aspect ratio of the interval between the interconnections 55 to the film thickness of the interconnections 55 is at 1 or higher. By this constitution, the silicon oxide film 56A can be deposited at high step coverage at a low temperature at which the aluminum alloy films 55B for the interconnections 55 are not melted.

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