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1. 发明专利

JPH08250683A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250683A
公开(公告)日：1996-09-27
申请号：JP6407796
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve an adhesion property between a base insulating film and a wiring, and improve processing accuracy of the wiring and a transition metal film underlying the wiring by forming a second metal film formed by a CVD process on a first metal film formed by a sputtering process. CONSTITUTION: This device comprises a plurality of wirings 55 consisting of an insulating film (base insulating film) 53 formed on a principal surface of a semiconductor substrate 20 and a metal film (transition metal film) 54 formed on the base insulating film 53. The transition metal film 54 includes a first metal film formed by a sputtering process and a second metal film formed by a CVD process. The second metal film is formed on the first metal film. The first metal film has its thickness thinner than that of the second metal film. The first and second metal films comprise the same material. Hereby, the transition metal film 54 deposited by a sputtering process has a higher adhesion property with each of the base insulating film 53 and the wiring 55 so that an adhesion property between the base insulating film 53 and the wiring 55 can be improved.

2. 发明专利

JPH08250682A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08250682A
公开(公告)日：1996-09-27
申请号：JP6407596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/108
摘要： PURPOSE: To reduce resistance of an interface between a transition metal film buried in a connection hole and an aluminum alloy wiring and hence reduce a disconnection failure of a wiring by providing a barrier layer between the transition metal film and the aluminum alloy wiring. CONSTITUTION: A semiconductor integrated circuit device includes a first wiring 52 formed on a semiconductor substrate 20, and an interlayer insulating film 53 having an opening (connection hole) through which part of the first wiring 52 is exposed and formed on the first wiring 52. It further includes a transition metal film 54 formed over the connection hole 53D in the interlayer insulating film 53 and an aluminum alloy wiring 55B containing an additive Si formed on the transition metal film 54 and the interlayer insulating film 53. Particularly, a barrier layer (transition metal silicide film) 55A is provided between the transition metal film 54 and the aluminum alloy wiring 55B. Hereby, the transition metal silicide film 55A can connect, even if the aluminum alloy wiring 55B is cut down owing to a migration phenomenon for example, the aluminum alloy wirings 55B putting the cut part therebetween, and can hence reduce a disconnection failure of a wiring.

3. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

4. 发明专利

JPH08250681A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250681A
公开(公告)日：1996-09-27
申请号：JP6407496
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE: To flatten the surface of an interlayer insulating film by filling an interval between lower electrode layers with an interlayer insulating layer by making thicker the thickness of the interlayer insulating film than the specific amount of a distance between first electrodes of a memory cell where the first electrodes of the memory cell adjoin with a minimum interval. CONSTITUTION: This device comprises a plurality of word lines 27 that constitute a gate electrode 27 of a memory cell selecting MISFETQS, a first electrode 37 extending onto the word lines, and a second electrode 35 provided oppositely to the first electrode 37 through a dielectric 36. An interlayer insulating film 53 is provided between a second electrode 37 and a wiring 36. The first electrode 37 is independently of each memory cell M, and the second electrode 35 is formed commonly to a plurality of the memory cells. The interlayer insulating film 53 is constructed to be thicker than 1/2 of a distance between the first electrodes 37 where the first electrodes of the memory cell M adjoin with a minimum interval. Hereby, an interval between the lower layer electrode layers 35 is filled with the interlayer insulating film 53 to flatten the surface of the interlayer insulating film 53.

5. 发明专利

JPH08250601A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250601A
公开(公告)日：1996-09-27
申请号：JP6404696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve hot carrier withstand voltage by making virtually equal the dimensions in the direction of gate length of the semiconductor regions of low impurity concentration, which form the LDD structure of a first and a second MISFETs, respectively. CONSTITUTION: The n-channel MISFETs Qn of an input/output stage circuit and an internal circuit are composed of a gate insulating film 26, a gate electrode 27, a n-type semiconductor region 29, and a n--type semiconductor region 32, respectively. The side wall spacers 31 of these n-channel MISFETs Qn are virtually the same in size in the direction of gate length. The gate length of the n-channel MISFET Qn in the input/output stage circuit is made larger than that of the n-channel MISFET Qn in the internal circuit. Further, the n-type semiconductor regions 29 forming the LDD structure of the n-channel MISFETs are virtually the same in size in the direction of gate length. This improves hot carrier withstand voltage, and reduces threshold voltage drop with a lapse of time, which enables the improvement of electrical characteristics.

6. 发明专利

JPH08241969A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241969A
公开(公告)日：1996-09-17
申请号：JP6407696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the moisture-proof of a passivation film formed on an interconnection layer by a method wherein the film thickness of an insulating film formed on an aluminum interconnection is specified by using a CVD method in which tetraethoxysilane is used as a source gas. CONSTITUTION: A passivation film 56 is formed on interconnections 55 which are composed mainly of aluminum alloy films 55B. The passivation film 56 is constituted of a composite film in which each of a silicon oxide film 56A deposited by a C-CVD method by using tetraethoxysilane as a source gas and a silicon nitride film 56B deposited by a plasma CVD method have been laminated in order. The silicon oxide film 56A at the lower layer of the passivation film 56 is constituted at a film thickness at 1/2 or higher of the interval between the interconnections 55 in regions in which the aspect ratio of the interval between the interconnections 55 to the film thickness of the interconnections 55 is at 1 or higher. By this constitution, the silicon oxide film 56A can be deposited at high step coverage at a low temperature at which the aluminum alloy films 55B for the interconnections 55 are not melted.

7. 发明专利

JPH0316153A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF AND APPARATUS FOR PRODUCTION THEREOF 失效
公开(公告)号：JPH0316153A
公开(公告)日：1991-01-24
申请号：JP6584989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To enhance an integration density by a method wherein a channel stopper region is formed in a main-face part under an insulating film for interelement isolation use of a substrate. CONSTITUTION:An oxidation-resistant mask whose film thickness is thin as compared with an oxidation-resistant mask of a first mask and an etching mask are laminated one after another; thereby, a second mask is formed. An etching treatment of a main face in an inert region of a substrate is executed by using the first and second masks; a groove is formed in the inert region of the substrate. Then, an oxidation treatment is executed by using the first and second masks; an insulating film for interelement isolation use (field insulating film) is formed on the main face of the inert region of the substrate. Then, the first and second masks are removed; after that, impurities are introduced into the whole main-face part including an active region and the inert region of the substrate; a channel stopper region is formed on the main-face part under the insulating film for interelement isolation use of the substrate. Thereby, an integration density can be enhanced.

8. 发明专利

JPH0236535A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0236535A
公开(公告)日：1990-02-06
申请号：JP18561888
申请日：1988-07-27
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI , HORIUCHI MITSUAKI
IPC分类号： H01L21/3205 , H01L21/316 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PURPOSE:To prevent the resistance value of copper wirings from increasing by covering the copper wirings with diffusion preventive film of impurity. CONSTITUTION:Diffusion preventive films 20a, 20b, 20c capable of preventing an impurity from diffusing are composed of a conductive film e.g., titanium nitride film. These diffusion preventive films 20a, 20b, 20c are connected to a paste leading-out electrode 13, a polycrystalline silicon emitter electrode 14 and a collector leading-out region 4 through openings 21a, 21b, 21c provided in insulating films 17, 18. Then, copper wirings 22a, 22b, 22c in the first layer are provided on these diffusion preventive films 20a, 20b, 20c. The impurity contained in the underneath insulating film 19 can be prevented from diffusing in the copper wirings 22a, 22b, 22c during the heat treatment process by the diffusion preventive films 20a, 20b, 20c. Furthermore, the bondability of the copper wirings 22a, 22b, 22c to the underneath film 19 can be enhanced by the diffusion preventive films 20a, 20b, 20c.

9. 发明专利

JPS6425439A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6425439A
公开(公告)日：1989-01-27
申请号：JP18145987
申请日：1987-07-21
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI , HORIUCHI MITSUAKI
IPC分类号： H01L21/768 , H01L21/31 , H01L21/3205 , H01L21/331 , H01L21/8222 , H01L23/52 , H01L23/522 , H01L23/532 , H01L27/06 , H01L29/73 , H01L29/732
摘要： PURPOSE:To prevent an impurity from diffusing in copper wirings externally at the time of heat treatment and to prevent the resistance value of the wirings from increasing by covering the wirings with an impurity diffusion preventive film. CONSTITUTION:Diffusion preventive films 20a, 20b, 20c which do not contain impurities, such as P, B and the like and can prevent the impurities from diffusing are composed of films having conductivity like a titanium nitride film. First layer copper wirings 22a, 22b, 22c are provided on the films 20a, 20b, 20c. Numeral 23 denotes a diffusion preventive film which does not contain the impurities, such as P, B and the like, can prevent the impurities from diffusing, and is formed of an insulating film like an SiO film formed by a plasma CVD. Further, a diffusion preventive film 25 made of an insulating film like an SiO film formed by the plasma CVD is formed on the film 24. Second layer copper wirings 26 are formed on the film 25.

10. 发明专利

JPS637364A BIAS SPUTTERING DEVICE 失效
公开(公告)号：JPS637364A
公开(公告)日：1988-01-13
申请号：JP14691086
申请日：1986-06-25
申请人： HITACHI LTD
发明人： OWADA NOBUO , HORIUCHI MITSUAKI , TSUNEOKA MASATOSHI
IPC分类号： H01L21/285 , C23C14/34
摘要： PURPOSE:To form a film which has excellent film quality and has excellent deposition property even on a pattern having a large aspect ratio by disposing a permanent magnet near a substrate in such a manner that the magnet can be moved back and forth in the plane direction of the substrate at the time of depositing a thin metallic film on the semiconductor substrate surface by a bias sputtering device. CONSTITUTION:An upper electrode 2 mounted with the Si wafer substrate W as a semiconductor and a lower electrode 3 mounted with a target T are disposed to face each other in a vacuum vessel. A prescribed bias voltage is impressed to the substrate W on the upper electrode 2 by a negative power source 4 and a negative power source 5 is connected to the lower electrode 3 as well as a cathode electrode. The permanent magnet 13 is fixed to the rear surface of the lower electrode 3 to generate a magnetic field near the target T. The permanent magnet 11 which generates the magnetic field near the target T and can move back and forth in the plane direction of the rear of the upper electrode 2 is mounted to an arm 10 and is moved relatively with the substrate W to uniformize the magnetic field to the substrate W, by which the plasma density near the substrate W is increased without increasing the bias voltage and the good-quality thin film of Al having the excellent deposition property is formed on the Si wafer substrate W.

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