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1. 发明专利

JPH11243108A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11243108A
公开(公告)日：1999-09-07
申请号：JP33930398
申请日：1998-11-30
申请人： HITACHI LTD
发明人： OWADA NOBUO , OOGAYA KAORU , KOBAYASHI TORU , KAWAJI MOTONORI
IPC分类号： H01L21/82 , H01L21/3205 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To improve the connection reliability of a solder bump. SOLUTION: Rectangular dummy patterns 8 formed of the same material as, for example, 3rd-layer Al wires 7a to 7d are provided at specific intervals in extra areas of the same wire layer with the 3rd-layer Al wires 7a to 7d. The dummy patterns 8 are arranged, where extra regions of the same layer with the 3rd-layer Al wires 7a to 7d and extra regions of the same layer with 2nd-layer Al wires 25a to 25f overlap with each other. Namely, the dummy patterns 8 are arranged individually on regions where wire channels of the same layer (3rd layer) and wire channels of the wire layer (2nd layer) directly below them cross each other. These dummy patterns 8 are formed in the same process by using the same mask as, for example, the 3rd-layer Al wires 7a to 7d.

2. 发明专利

JP2579999B2 失效
公开(公告)号：JP2579999B2
公开(公告)日：1997-02-12
申请号：JP11465088
申请日：1988-05-13
申请人： HITACHI LTD
发明人： NISHIZAWA HIROTAKA , KAWAJI MOTONORI , TAKAKURA TOSHIHIKO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732

3. 发明专利

JPH06160469A SEMICONDUCTOR DEVICE AND ITS TESTING METHOD 失效
公开(公告)号：JPH06160469A
公开(公告)日：1994-06-07
申请号：JP30848992
申请日：1992-11-18
申请人： HITACHI LTD
发明人： NONAMI HIDEAKI , KAWAJI MOTONORI
IPC分类号： G01R31/26 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To reduce the manufacturing cost of a testing device used for burn-in tests so as to reduce the cost of a high-speed logic integrated circuit device by reducing the kinds of power supply voltages applied at the time of performing burn-in tests on the high-speed logic integrated circuit device, etc., which requires a plurality kinds of power supply voltages and is provided with a plurality of power supply terminals to which the power supply voltages are supplied. CONSTITUTION:Voltage conversion circuits VC1 and VC2 which form power supply voltages VEEL and VTT of different potentials based on a power supply voltage VESL which is selectively made effective at the time of burn-in tests and has, for example, the maximum absolute value are incorporated in the LSI of a high-speed logic integrated circuit device, etc.

4. 发明专利

JPH0564457B2 失效
公开(公告)号：JPH0564457B2
公开(公告)日：1993-09-14
申请号：JP8402884
申请日：1984-04-27
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KAWAJI MOTONORI , ANZAI AKIO , KURODA SHIGEO , SAKAI TETSUSHI
IPC分类号： H01L21/30 , H01L21/027 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/732

5. 发明专利

JPH0562464B2 失效
公开(公告)号：JPH0562464B2
公开(公告)日：1993-09-08
申请号：JP24381783
申请日：1983-12-26
申请人： HITACHI LTD
发明人： KAWAJI MOTONORI , TAKAKURA TOSHIHIKO , UCHIDA AKIHISA
IPC分类号： H01L21/3205 , H01L21/76 , H01L23/52

6. 发明专利

JPH0544183B2 失效
公开(公告)号：JPH0544183B2
公开(公告)日：1993-07-05
申请号：JP24380883
申请日：1983-12-26
申请人： HITACHI LTD
发明人： NISHIZAWA HIROTAKA , KURODA SHIGEO , KAWAJI MOTONORI , WATANABE KUNIHIKO , TAKAKURA TOSHIHIKO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732

7. 发明专利

JPS6126224A Method for process of minute hole 失效
标题翻译：小孔过程方法
公开(公告)号：JPS6126224A
公开(公告)日：1986-02-05
申请号：JP14684984
申请日：1984-07-17
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： KAWAJI MOTONORI , KURODA SHIGEO , ANZAI AKIO , SAKAI TETSUSHI
IPC分类号： H01L21/22 , H01L21/302 , H01L21/306 , H01L21/3065
CPC分类号： H01L21/302
摘要： PURPOSE:To arrange minute holes on an insulating film surely with high accuracy by utilizing the fact that the polysilicon which does not includes B is removed selectively from the polysilicon doped with B by hydrazine liquid. CONSTITUTION:Polysilicon 3 including B is laminated on an SiO2 film 2 of an Si substrate 1 and a hole 3a of the same size as a window 4a of a resist mask is formed on the polysilicon 3. The resist is removed and the non-doped polysilicon 5 is laminated. By heat treatment, B is diffused from the layer 3 to the layer 5 and a non-doped layer 5 is formed inside of hole 3a by controlling temperature and time with high acuracy. Only layer 5a is etched by hydrazine to form a minute hole 6. By this constitution, if a diameter of the window 3a of resist is determined to be the minimum size by photographing technique, the minute hole 6 having a smaller diameter than that can be formed.
摘要翻译：目的：通过利用不含B的多晶硅选择性地通过肼液体从B掺杂的多晶硅中高精度地安排绝缘膜上的微孔。构成：将包含B的多晶硅3层叠在Si衬底1的SiO 2膜2上，并且在多晶硅3上形成与抗蚀剂掩模的窗口4a相同尺寸的孔3a。去除抗蚀剂并将非掺杂层压多晶硅5。通过热处理，B从层3扩散到层5，并且通过以高的锐度控制温度和时间，在孔3a内部形成非掺杂层5。仅通过肼蚀刻层5a以形成微孔6.通过这种结构，如果通过拍摄技术将抗蚀剂的窗口3a的直径确定为最小尺寸，则具有比其小的直径的微孔6 形成。

8. 发明专利

JPS60229370A MANUFACTURE OF SELF-ALIGNMENT TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60229370A
公开(公告)日：1985-11-14
申请号：JP8402884
申请日：1984-04-27
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KAWAJI MOTONORI , ANZAI AKIO , KURODA SHIGEO , SAKAI TETSUSHI
IPC分类号： H01L21/30 , H01L21/027 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To improve the accuracy of a semiconductor region up to a value smaller than minimum resolution size by photolithography by fining a pattern obtained through a normal photolithography technique through annealing treatment for diffusing an impurity. CONSTITUTION:An insulating isolating region 15, a semiconductor region 22 and a contact hole to a semiconductor region separate from the semiconductor region 22 are formed on the same masks 90-93 in a self-alignment manner. When an impurity such as boron is introduced into polycrystalline silicon 7, the generation of a difference between etching rates due to the difference of impurity concentration is utilized, and a pattern obtained through photo-resist treatment is fined through annealing treatment for diffusing the impurity.

9. 发明专利

JPS60128633A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60128633A
公开(公告)日：1985-07-09
申请号：JP23613483
申请日：1983-12-16
申请人： HITACHI LTD
发明人： KAWAJI MOTONORI , KURODA SHIGEO , NISHIZAWA HIROTAKA , TAKAKURA TOSHIHIKO
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/76 , H01L27/06 , H01L29/73 , H01L29/732
摘要： PURPOSE:To obtain the element isolated structure of small electrostatic capacitance in which an element wiring can be performed in the region of this thick oxide film by a method wherein an isolation groove, the inside surface of which is covered by an insulating tilm, and the relatively thick oxide film formed on the surface of a semiconductor substrate are adjoiningly formed. CONSTITUTION:An arbitrary element 35 is isolated by a groove 33, and an element 36 is isolated by thick oxide films 32a and 32b. A polycrystalline silicon oxide film 27 is formed on the element 35 isolated by the groove 33 and the region containing a boundary part 29a. Before the formation of thick oxide films 32a and 32b, a sand etching is performed on the polycrystalline oxide film 29, and a groove having the width smaller than the minimum working measurements of photolithography is formed close to the thick oxide film 32a. The width of said groove 33 is determined by the amount of side etching performed on the polycrystalline silicon oxide film 29 and the extent of extension in lateral direction of the oxide film 32.

10. 发明专利

JPS59217373A Manufacture of schottky gate type field effect transistor 失效
标题翻译：肖特基门型场效应晶体管的制造
公开(公告)号：JPS59217373A
公开(公告)日：1984-12-07
申请号：JP9066983
申请日：1983-05-25
申请人： Hitachi Ltd
发明人： KAWAJI MOTONORI , ENOMOTO MINORU , TAKAHASHI TAKAHIKO , KURODA SHIGEO , ANZAI AKIO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/417 , H01L29/80 , H01L21/28
CPC分类号： H01L29/80
摘要： PURPOSE:To reduce the parasitic series resistance by a method wherein the gate, source and drain are put in self-alignment by side etching and lift-off, thus reducing each interval to the short distance only by that corresponding to the side etching amount. CONSTITUTION:An N type GaAs layer 2 is formed on a semi-insulation GaAs substrate 1 only at the part for element formation. Next, an N type GaAs layer 3 and an Si nitride layer 4 are successively laminated over the entire surface of the substrate 1. Then, the part serving as the gate of a lift-off material layer 4 is removed, and, with the layer 4 as a mask, a high concentration semiconductor layer 3 is etched, thus forming a groove 5. Thereafter, when gate metallic material 6 is deposited, said material is formed with step cuts, which material lifts off the part attached on the layer 4 by etching the layer 4, and then turns to a gate metallic film 61. After removing the layer 3 except for that of the element, a passivation insulation film 7 is formed over the entire surface, holes 81, 82 and 83 are opened, and the source electrode 91, drain electrode 92, and gate electrode lead-out electrode and wiring are formed. Thereby, the device can be speeded up by reducing the parasitic series resistance.
摘要翻译：目的：为了减少寄生串联电阻，其方法是通过侧面蚀刻和剥离将栅极，源极和漏极置于自对准状态，从而将每个间隔减小到相当于侧面蚀刻量的距离。构成：仅在元件形成部分的半绝缘GaAs衬底1上形成N +型GaAs层2。接着，在衬底1的整个表面上依次层叠N +型GaAs层3和氮化硅层4，然后，除去作为剥离材料层4的栅极的部分，以层4作为掩模，蚀刻高浓度半导体层3，从而形成凹槽5.此后，当沉积栅极金属材料6时，所述材料形成有阶梯切割，该材料从附着在其上的部分通过蚀刻层4，然后转到栅极金属膜61.除去除了元件之外的层3之后，在整个表面上形成钝化绝缘膜7，打开孔81,82和83 ，并且形成源电极91，漏电极92和栅电极引出电极和布线。因此，可以通过减小寄生串联电阻来加速装置。

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