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1. 发明专利

JPH08250682A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08250682A
公开(公告)日：1996-09-27
申请号：JP6407596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/108
摘要： PURPOSE: To reduce resistance of an interface between a transition metal film buried in a connection hole and an aluminum alloy wiring and hence reduce a disconnection failure of a wiring by providing a barrier layer between the transition metal film and the aluminum alloy wiring. CONSTITUTION: A semiconductor integrated circuit device includes a first wiring 52 formed on a semiconductor substrate 20, and an interlayer insulating film 53 having an opening (connection hole) through which part of the first wiring 52 is exposed and formed on the first wiring 52. It further includes a transition metal film 54 formed over the connection hole 53D in the interlayer insulating film 53 and an aluminum alloy wiring 55B containing an additive Si formed on the transition metal film 54 and the interlayer insulating film 53. Particularly, a barrier layer (transition metal silicide film) 55A is provided between the transition metal film 54 and the aluminum alloy wiring 55B. Hereby, the transition metal silicide film 55A can connect, even if the aluminum alloy wiring 55B is cut down owing to a migration phenomenon for example, the aluminum alloy wirings 55B putting the cut part therebetween, and can hence reduce a disconnection failure of a wiring.

2. 发明专利

JPH08250681A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250681A
公开(公告)日：1996-09-27
申请号：JP6407496
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE: To flatten the surface of an interlayer insulating film by filling an interval between lower electrode layers with an interlayer insulating layer by making thicker the thickness of the interlayer insulating film than the specific amount of a distance between first electrodes of a memory cell where the first electrodes of the memory cell adjoin with a minimum interval. CONSTITUTION: This device comprises a plurality of word lines 27 that constitute a gate electrode 27 of a memory cell selecting MISFETQS, a first electrode 37 extending onto the word lines, and a second electrode 35 provided oppositely to the first electrode 37 through a dielectric 36. An interlayer insulating film 53 is provided between a second electrode 37 and a wiring 36. The first electrode 37 is independently of each memory cell M, and the second electrode 35 is formed commonly to a plurality of the memory cells. The interlayer insulating film 53 is constructed to be thicker than 1/2 of a distance between the first electrodes 37 where the first electrodes of the memory cell M adjoin with a minimum interval. Hereby, an interval between the lower layer electrode layers 35 is filled with the interlayer insulating film 53 to flatten the surface of the interlayer insulating film 53.

3. 发明专利

JPH08250601A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250601A
公开(公告)日：1996-09-27
申请号：JP6404696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve hot carrier withstand voltage by making virtually equal the dimensions in the direction of gate length of the semiconductor regions of low impurity concentration, which form the LDD structure of a first and a second MISFETs, respectively. CONSTITUTION: The n-channel MISFETs Qn of an input/output stage circuit and an internal circuit are composed of a gate insulating film 26, a gate electrode 27, a n-type semiconductor region 29, and a n--type semiconductor region 32, respectively. The side wall spacers 31 of these n-channel MISFETs Qn are virtually the same in size in the direction of gate length. The gate length of the n-channel MISFET Qn in the input/output stage circuit is made larger than that of the n-channel MISFET Qn in the internal circuit. Further, the n-type semiconductor regions 29 forming the LDD structure of the n-channel MISFETs are virtually the same in size in the direction of gate length. This improves hot carrier withstand voltage, and reduces threshold voltage drop with a lapse of time, which enables the improvement of electrical characteristics.

4. 发明专利

JPH08241969A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241969A
公开(公告)日：1996-09-17
申请号：JP6407696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the moisture-proof of a passivation film formed on an interconnection layer by a method wherein the film thickness of an insulating film formed on an aluminum interconnection is specified by using a CVD method in which tetraethoxysilane is used as a source gas. CONSTITUTION: A passivation film 56 is formed on interconnections 55 which are composed mainly of aluminum alloy films 55B. The passivation film 56 is constituted of a composite film in which each of a silicon oxide film 56A deposited by a C-CVD method by using tetraethoxysilane as a source gas and a silicon nitride film 56B deposited by a plasma CVD method have been laminated in order. The silicon oxide film 56A at the lower layer of the passivation film 56 is constituted at a film thickness at 1/2 or higher of the interval between the interconnections 55 in regions in which the aspect ratio of the interval between the interconnections 55 to the film thickness of the interconnections 55 is at 1 or higher. By this constitution, the silicon oxide film 56A can be deposited at high step coverage at a low temperature at which the aluminum alloy films 55B for the interconnections 55 are not melted.

5. 发明专利

JPH0316153A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF AND APPARATUS FOR PRODUCTION THEREOF 失效
公开(公告)号：JPH0316153A
公开(公告)日：1991-01-24
申请号：JP6584989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To enhance an integration density by a method wherein a channel stopper region is formed in a main-face part under an insulating film for interelement isolation use of a substrate. CONSTITUTION:An oxidation-resistant mask whose film thickness is thin as compared with an oxidation-resistant mask of a first mask and an etching mask are laminated one after another; thereby, a second mask is formed. An etching treatment of a main face in an inert region of a substrate is executed by using the first and second masks; a groove is formed in the inert region of the substrate. Then, an oxidation treatment is executed by using the first and second masks; an insulating film for interelement isolation use (field insulating film) is formed on the main face of the inert region of the substrate. Then, the first and second masks are removed; after that, impurities are introduced into the whole main-face part including an active region and the inert region of the substrate; a channel stopper region is formed on the main-face part under the insulating film for interelement isolation use of the substrate. Thereby, an integration density can be enhanced.

6. 发明专利

JPH09245485A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09245485A
公开(公告)日：1997-09-19
申请号：JP4881796
申请日：1996-03-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISODA MASANORI , TANAKA HITOSHI , SAKATA TAKESHI , KIMURA KATSUTAKA , TORII KAZUNARI
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To return an electric field applied to a ferroelectric capacitor to zero accurately to initialize characteristics by a pulse that is not prescribed by conditions such as temperature and stress in a ferrodielectric memory. SOLUTION: In the initialization, switches Sot and Sob are opened and switches Sdt and/or Sdb are closed to connect an attenuation vibration circuit DP to an IO wire. Ferrodielectric capacitors CO-Cn are selected by a line selection signal YSn and required word lines WO-Wn to apply an output Dpo of the attenuation vibration circuit. A potential of a plate line PL is shifted to an intermediate potential of the output Dpo by a plate voltage source VR. The voltage amplitude of the output pulse Dpo is gradually attenuated to turn an electric field applied to the capacitor to zero finally. In the normal operation, the switches Sot and Sob are closed and the switches Sdt and Sdb are opened. Thus, improved degrading in characteristic of the ferrodielectric allows reduction in malfunctioning of the ferroelectric memory thereby enhancing the reliability of a system.

7. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

8. 发明专利

JPH08250683A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250683A
公开(公告)日：1996-09-27
申请号：JP6407796
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L23/522 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve an adhesion property between a base insulating film and a wiring, and improve processing accuracy of the wiring and a transition metal film underlying the wiring by forming a second metal film formed by a CVD process on a first metal film formed by a sputtering process. CONSTITUTION: This device comprises a plurality of wirings 55 consisting of an insulating film (base insulating film) 53 formed on a principal surface of a semiconductor substrate 20 and a metal film (transition metal film) 54 formed on the base insulating film 53. The transition metal film 54 includes a first metal film formed by a sputtering process and a second metal film formed by a CVD process. The second metal film is formed on the first metal film. The first metal film has its thickness thinner than that of the second metal film. The first and second metal films comprise the same material. Hereby, the transition metal film 54 deposited by a sputtering process has a higher adhesion property with each of the base insulating film 53 and the wiring 55 so that an adhesion property between the base insulating film 53 and the wiring 55 can be improved.

9. 发明专利

JP2003303963A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003303963A
公开(公告)日：2003-10-24
申请号：JP2002108944
申请日：2002-04-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： GOTO YASUSHI , TORII KAZUNARI , YOKOYAMA NATSUKI
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve the planarity of a semiconductor device using a substitution gate process, and to increase its reliability.
SOLUTION: A shallow groove element isolation region 402, an n-type transistor region 409, and a p-type transistor region 416 are formed on a silicon substrate 401. Dummy gate insulating films 403 and dummy gate electrodes 404 are formed on the regions. Sidewall spacers 405 are formed on the sidewalls. A silicon nitride film 407 and an interlayer film 408 are formed on the silicon substrate 401. The films (408, 407) are polished by CMP, until the upper surface of the dummy gate electrode 404 is exposed. The dummy gate electrode 404 and the dummy gate insulating film 403 of the n-type transistor region 409 are removed. The gate insulating film, having a high dielectric constant and a gate electrode material, is embedded between the sidewall spacers 405 of the n-type transistor region 409.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提高使用替代栅极工艺的半导体器件的平面性，并提高其可靠性。解决方案：在硅衬底401上形成浅沟槽元件隔离区域402，n型晶体管区域409和p型晶体管区域416.将虚拟栅极绝缘膜403和伪栅极电极404形成在地区。侧壁间隔件405形成在侧壁上。在硅衬底401上形成氮化硅膜407和层间膜40.通过CMP对膜（408,407）进行抛光，直到伪栅电极404的上表面露出。去除n型晶体管区域409的伪栅电极404和伪栅极绝缘膜403。具有高介电常数的栅极绝缘膜和栅电极材料被嵌入在n型晶体管区域409的侧壁间隔物405之间。（C）2004，JPO

10. 发明专利

JPH1140773A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH1140773A
公开(公告)日：1999-02-12
申请号：JP19615797
申请日：1997-07-22
申请人： HITACHI LTD
发明人： MIKI HIROSHI , TORII KAZUNARI , FUJISAKI YOSHIHISA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a new semiconductor storage device for which the area increase caused by capacitor machining can be suppressed, when a material including lead or bismuth is used for the dielectric film of a capacitor. SOLUTION: Lower electrodes 103 are separated for each cell and are formed, and then the area between the electrodes is buried by an insulator film 102, a dielectric film 104 consisting of a material including at least lead or bismuth is continuously formed over a plurality of cells, and an area above the dielectric film 104 is covered with an upper electrode 105. The oxide of a metal element with at least quadrivalent valence in an element for constituting the dielectric film 104 is used as the material of the insulator film 102, thus reducing a region for separating memory cells and hence improving integration.

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