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    • 1. 发明申请
    • Secure Dynamically Reconfigurable Logic
    • 安全动态可重构逻辑
    • US20120005473A1
    • 2012-01-05
    • US12827726
    • 2010-06-30
    • H. Peter HofsteeJames A. KahleMichael A. Paolini
    • H. Peter HofsteeJames A. KahleMichael A. Paolini
    • G06F1/24
    • G06F21/76G06F15/7867
    • A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.
    • 提供了一种用于安全和动态地重新配置可重构逻辑的机制。 数据处理系统内的状态机为数据处理系统内的可重构逻辑建立硬件边界,从而形成隔离的可重配置逻辑。 状态机清除分离的可重新配置逻辑中存在的任何先前状态。 状态机验证要加载到隔离可重配置逻辑中的新配置。 状态机确定新配置的认证是否成功。 响应于新配置的认证成功,状态机将新配置加载到隔离的可重配置逻辑中。 状态机然后启动隔离的可重新配置逻辑的操作。
    • 2. 发明授权
    • Secure dynamically reconfigurable logic
    • 安全动态可重构逻辑
    • US08516272B2
    • 2013-08-20
    • US12827726
    • 2010-06-30
    • H Peter HofsteeJames A. KahleMichael A. Paolini
    • H Peter HofsteeJames A. KahleMichael A. Paolini
    • G06F11/30G06F15/16G06F15/177H04L12/28H04J3/02H04J3/16H04K1/00
    • G06F21/76G06F15/7867
    • A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.
    • 提供了一种用于安全和动态地重新配置可重构逻辑的机制。 数据处理系统内的状态机为数据处理系统内的可重构逻辑建立硬件边界,从而形成隔离的可重配置逻辑。 状态机清除分离的可重新配置逻辑中存在的任何先前状态。 状态机验证要加载到隔离可重配置逻辑中的新配置。 状态机确定新配置的认证是否成功。 响应于新配置的认证成功,状态机将新配置加载到隔离的可重配置逻辑中。 状态机然后启动隔离的可重新配置逻辑的操作。
    • 10. 发明授权
    • Method and processor that permit concurrent execution of a store
multiple instruction and a dependent instruction
    • 允许并发执行存储多指令和依赖指令的方法和处理器
    • US5867684A
    • 1999-02-02
    • US873013
    • 1997-06-11
    • James A. KahleAlbert J. LoperSoummya MallickAubrey D. Ogden
    • James A. KahleAlbert J. LoperSoummya MallickAubrey D. Ogden
    • G06F9/312G06F9/38G06F12/00
    • G06F9/30043G06F9/3824G06F9/3834G06F9/3838
    • A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.
    • 提供了一种在超标量微处理器中执行加载多指令的方法和装置。 该方法包括以下步骤:向加载/存储单元发送加载多个指令,其中加载/存储单元开始执行分派的加载多个指令,并且其中加载多个指令将数据从存储器加载到多个寄存器中。 该方法还包括维护列出多个寄存器的每个寄存器并且通过执行加载多个指令指示何时将数据加载到每个寄存器中的表的步骤。 该方法通过在载入多个指令完成其执行之前执行依赖于由加载多个指令加载的源操作数数据到由指令指示的多个寄存器的寄存器中作为源寄存器的指令,当该表 表示源操作数数据已加载到源寄存器中。 此外,根据本发明,提供了一种在超标量微处理器中执行存储多重指令的方法。 该方法包括以下步骤:将存储多重指令分派到加载/存储单元,从而加载/存储单元开始执行存储多指令,其中加载存储指令将数据从多个寄存器存储到存储器; 并且在存储多个指令完成其执行之前,执行依赖于由所述固定点指令指示的多个寄存器的寄存器作为源寄存器的存储多个指令存储的数据的固定点指令,但是禁止 在存储多个指令完成之前,从写入到多个寄存器的寄存器执行固定点指令。