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1. 发明授权

US09268598B2 Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories 有权
标题翻译：记录和分析交易失败源地址和对应于硬件事务存储器中止事务的地址的有效性指示符
公开(公告)号：US09268598B2
公开(公告)日：2016-02-23
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46 , G06F11/14 , G06F11/36
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

2. 发明授权

US08386753B2 Completion arbitration for more than two threads based on resource limitations 有权
标题翻译：根据资源限制完成多于两个线程的仲裁
公开(公告)号：US08386753B2
公开(公告)日：2013-02-26
申请号：US12423561
申请日：2009-04-14
申请人： Susan E. Eisen , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
发明人： Susan E. Eisen , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
IPC分类号： G06F9/38
CPC分类号： G06F9/485
摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.
摘要翻译：提供线程完成仲裁的机制。该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程的线程，在两个以上的线程中，用于完成处理器内的执行。该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。线程的第一个子集和线程的第二个子集具有彼此不同的线程。

3. 发明申请

US20140075441A1 METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES 有权
标题翻译：硬件交易记录中记录和分类交易失败源地址的方法和装置
公开(公告)号：US20140075441A1
公开(公告)日：2014-03-13
申请号：US13615416
申请日：2012-09-13
申请人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
发明人： Robert J. Blainey , Harold W. Cain , Susan E. Eisen , Bradly G. Frey , Charles B. Hall , Hung Q. Le , Cathy May
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F11/1474 , G06F11/36 , G06F11/3648
摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
摘要翻译：处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。事务存储器存储由处理器核心执行的多个事务的信息。处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

4. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

5. 发明授权

US08725993B2 Thread transition management 失效
标题翻译：线程转换管理
公开(公告)号：US08725993B2
公开(公告)日：2014-05-13
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

6. 发明申请

US20100262806A1 Tracking Effective Addresses in an Out-of-Order Processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

7. 发明授权

US10067765B2 Speeding up younger store instruction execution after a sync instruction 有权
公开(公告)号：US10067765B2
公开(公告)日：2018-09-04
申请号：US13470386
申请日：2012-05-14
申请人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
发明人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
IPC分类号： G06F9/38 , G06F9/30
摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

8. 发明申请

US20130305022A1 Speeding Up Younger Store Instruction Execution after a Sync Instruction 审中-公开
标题翻译：加快同步指令后的较小的存储指令执行
公开(公告)号：US20130305022A1
公开(公告)日：2013-11-14
申请号：US13470386
申请日：2012-05-14
申请人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
发明人： Susan E. Eisen , Hung Q. Le , Bryan J. Lloyd , Dung Q. Nguyen , David S. Ray , Benjamin W. Stolt , Shih-Hsiung S. Tung
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3824 , G06F9/3834 , G06F9/3857 , G06F9/3861
摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
摘要翻译：在处理器中提供用于执行比先前调度的同步（sync）指令更年轻的指令的机制。处理器的指令定序器单元调度同步指令。同步指令被发送到处理器外部的一个或多个设备的嵌套。指令定序器单元在调度同步指令之后调度后续指令。调度同步指令后的后续指令的调度是在收到来自嵌套的同步确认响应之前执行的。指令定序器单元基于后续指令的完成是否依赖于从嵌套接收到同步确认和完成同步指令而执行后续指令的完成。

9. 发明申请

US20120216004A1 THREAD TRANSITION MANAGEMENT 失效
标题翻译：螺纹过渡管理
公开(公告)号：US20120216004A1
公开(公告)日：2012-08-23
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F12/02
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

10. 发明申请

US20100262967A1 Completion Arbitration for More than Two Threads Based on Resource Limitations 有权
标题翻译：基于资源限制的两个以上线程的完成仲裁
公开(公告)号：US20100262967A1
公开(公告)日：2010-10-14
申请号：US12423561
申请日：2009-04-14
申请人： Susan E. Eisen , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
发明人： Susan E. Eisen , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.
摘要翻译：提供线程完成仲裁的机制。该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程的线程，在两个以上的线程中，用于完成处理器内的执行。该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。线程的第一个子集和线程的第二个子集具有彼此不同的线程。

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