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1. 发明申请

US20110154107A1 TRIGGERING WORKAROUND CAPABILITIES BASED ON EVENTS ACTIVE IN A PROCESSOR PIPELINE 有权
标题翻译：根据处理器管道中活动的事件触发替代能力
公开(公告)号：US20110154107A1
公开(公告)日：2011-06-23
申请号：US12645771
申请日：2009-12-23
申请人： GREGORY W. ALEXANDER , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： GREGORY W. ALEXANDER , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/14 , G06F11/07 , G06F9/312 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw.
摘要翻译：处理器中的处理缺陷的方法，信息处理系统和处理器。从存储器位置获取至少一个指令。至少一条指令被解码。响应于解码，将操作码比较操作与至少一个操作码比较寄存器中的至少一个指令和一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。

2. 发明授权

US08082467B2 Triggering workaround capabilities based on events active in a processor pipeline 有权
标题翻译：根据处理器管道中活动的事件触发解决方法的功能
公开(公告)号：US08082467B2
公开(公告)日：2011-12-20
申请号：US12645771
申请日：2009-12-23
申请人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/00
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.
摘要翻译：公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。从存储器位置获取至少一个指令。该指令被解码。与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

3. 发明授权

US09104399B2 Dual issuing of complex instruction set instructions 有权
标题翻译：双重发出复杂的指令集指令
公开(公告)号：US09104399B2
公开(公告)日：2015-08-11
申请号：US12645716
申请日：2009-12-23
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译：一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。指令发布单元向第一执行单元发出第一微操作以产生中间数据。然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。在延迟之后，向第二执行单元发出第二个微操作。

4. 发明申请

US20110153991A1 DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS 有权
标题翻译：复杂指令设置指令的双重发布
公开(公告)号：US20110153991A1
公开(公告)日：2011-06-23
申请号：US12645716
申请日：2009-12-23
申请人： FADI BUSABA , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： FADI BUSABA , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译：一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。指令发布单元向第一执行单元发出第一微操作以产生中间数据。然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。在延迟之后，向第二执行单元发出第二个微操作。

5. 发明授权

US09075600B2 Program status word dependency handling in an out of order microprocessor design 有权
标题翻译：程序状态字依赖处理在一个无序的微处理器设计
公开(公告)号：US09075600B2
公开(公告)日：2015-07-07
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译：一种处理计算机程序指令的计算机实现方法。该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。

6. 发明申请

US20110320782A1 PROGRAM STATUS WORD DEPENDENCY HANDLING IN AN OUT OF ORDER MICROPROCESSOR DESIGN 有权
标题翻译：程序状态字依赖于处理订单微处理器设计
公开(公告)号：US20110320782A1
公开(公告)日：2011-12-29
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/318
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译：一种处理计算机程序指令的计算机实现方法。该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。

7. 发明申请

US20090217009A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS 有权
标题翻译：用于转储储存元件的系统，方法和计算机程序产品
公开(公告)号：US20090217009A1
公开(公告)日：2009-08-27
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/318
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

8. 发明申请

US20090210662A1 MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM 有权
标题翻译： MICROPROCESSOR，方法和计算机程序产品，用于在MILLICODE可编程计算机系统中直接提取
公开(公告)号：US20090210662A1
公开(公告)日：2009-08-20
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译：配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。提供了一种方法和计算机程序产品。

9. 发明授权

US08549255B2 Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权
标题翻译：微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取
公开(公告)号：US08549255B2
公开(公告)日：2013-10-01
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译：配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。提供了一种方法和计算机程序产品。

10. 发明授权

US5764970A Method and apparatus for supporting speculative branch and link/branch on count instructions 失效
标题翻译：在计数指令上支持推测分支和链接/分支的方法和装置
公开(公告)号：US5764970A
公开(公告)日：1998-06-09
申请号：US560614
申请日：1995-11-20
申请人： Deepak Rana , David A. Schroter
发明人： Deepak Rana , David A. Schroter
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3863 , G06F9/384 , G06F9/3842
摘要： A method and apparatus for supporting speculative execution of count and link register modifying instructions in a microprocessor is provided. The apparatus includes a queue of rename buffers storing count/link register operand data resulting from speculatively executed instructions that modify a count/link register. The queue contains a set of control buffers, wherein each control buffer contains control bits associated with a rename buffer, the control bits including an instruction identifier tag identifying a speculatively executed instruction, the operand data of the speculatively executed instruction being stored in the associated rename buffer, and an available bit indicating when the operand data no longer needs to be stored in the associated rename buffer. The apparatus control logic sets the control bits for each control buffer, including setting the instruction identifier tag to the value indicated by a dispatch unit, and selectively sets or resets the available bit based on resolution of the speculatively executed instruction.
摘要翻译：提供了一种用于在微处理器中支持计数和链接寄存器修改指令的推测执行的方法和装置。该装置包括一个重命名缓冲器队列，存储由推测性地执行的修改计数/链接寄存器的指令产生的计数/链接寄存器操作数数据。队列包括一组控制缓冲器，其中每个控制缓冲器包含与重命名缓冲器相关联的控制位，控制位包括标识推测性执行的指令的指令标识符标签，被推测执行的指令的操作数数据存储在相关联的重命名缓冲区，以及指示何时操作数数据不再需要存储在关联的重命名缓冲区中的可用位。设备控制逻辑设置每个控制缓冲器的控制位，包括将指令标识符标签设置为由调度单元指示的值，并且基于推测执行的指令的分辨率选择性地设置或复位可用位。

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