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1. 发明授权

US08082467B2 Triggering workaround capabilities based on events active in a processor pipeline 有权
标题翻译：根据处理器管道中活动的事件触发解决方法的功能
公开(公告)号：US08082467B2
公开(公告)日：2011-12-20
申请号：US12645771
申请日：2009-12-23
申请人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/00
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.
摘要翻译：公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。从存储器位置获取至少一个指令。该指令被解码。与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

2. 发明申请

US20110154107A1 TRIGGERING WORKAROUND CAPABILITIES BASED ON EVENTS ACTIVE IN A PROCESSOR PIPELINE 有权
标题翻译：根据处理器管道中活动的事件触发替代能力
公开(公告)号：US20110154107A1
公开(公告)日：2011-06-23
申请号：US12645771
申请日：2009-12-23
申请人： GREGORY W. ALEXANDER , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： GREGORY W. ALEXANDER , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/14 , G06F11/07 , G06F9/312 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw.
摘要翻译：处理器中的处理缺陷的方法，信息处理系统和处理器。从存储器位置获取至少一个指令。至少一条指令被解码。响应于解码，将操作码比较操作与至少一个操作码比较寄存器中的至少一个指令和一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。

3. 发明授权

US09104399B2 Dual issuing of complex instruction set instructions 有权
标题翻译：双重发出复杂的指令集指令
公开(公告)号：US09104399B2
公开(公告)日：2015-08-11
申请号：US12645716
申请日：2009-12-23
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译：一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。指令发布单元向第一执行单元发出第一微操作以产生中间数据。然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。在延迟之后，向第二执行单元发出第二个微操作。

4. 发明申请

US20060179290A1 System and method for creating precise exceptions 失效
标题翻译：用于创建精确异常的系统和方法
公开(公告)号：US20060179290A1
公开(公告)日：2006-08-10
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Busaba , Michael Mack , John Rell , Eric Schwarz , Chung-Lung Shum , Timothy Slegel , Scott Swaney , Sheryll Veneracion
发明人： Fadi Busaba , Michael Mack , John Rell , Eric Schwarz , Chung-Lung Shum , Timothy Slegel , Scott Swaney , Sheryll Veneracion
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译：一种用于创建精确异常的方法，包括检查指向引起异常的指令。检查点导致当前检查点状态。当前检查点状态被锁定。确定多个寄存器中的任一个是否需要恢复到当前检查点状态。响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

5. 发明授权

US08938605B2 Instruction cracking based on machine state 有权
标题翻译：基于机器状态的指令开裂
公开(公告)号：US08938605B2
公开(公告)日：2015-01-20
申请号：US12718685
申请日：2010-03-05
申请人： Fadi Busaba , Bruce Giamei , David Hutton , Eric Schwarz
发明人： Fadi Busaba , Bruce Giamei , David Hutton , Eric Schwarz
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/342 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30189
摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.
摘要翻译：一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。至少接收一条指令。至少一条指令被解码。响应于解码确定当前机器状态。基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。执行一组操作单元。

6. 发明授权

US08495341B2 Instruction length based cracking for instruction of variable length storage operands 有权
标题翻译：指令长度为可变长度存储操作数指令的破解
公开(公告)号：US08495341B2
公开(公告)日：2013-07-23
申请号：US12707163
申请日：2010-02-17
申请人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
发明人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30149 , G06F9/3016 , G06F9/3017
摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。接收至少一个可变操作数长度指令。分析至少一个可变操作数长度指令。基于分析来识别可变操作数长度指令中的至少一个操作数的长度。所述至少一个可变操作数长度指令被组织成一组操作单元。执行操作单元的集合。所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

7. 发明申请

US20110185158A1 HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES 有权
标题翻译：用于存储多项指令的历史和对齐基础打破优化操作存储比较罚款
公开(公告)号：US20110185158A1
公开(公告)日：2011-07-28
申请号：US12695687
申请日：2010-01-28
申请人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
发明人： KHARY J. ALEXANDER , Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , James R. Mitchell
IPC分类号： G06F9/40
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3824 , G06F9/3838
摘要： Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
摘要翻译：存储多个指令是根据以前的执行历史及其对齐方式进行管理的。检测到至少一个存储多重指令。确定标志与至少一个存储多重指令相关联。该标志指示至少一个存储多指令先前已经遇到操作数存储比较危险。将至少一个存储多个指令组织成一组操作单元。执行一组操作单元。该执行避免了由至少一个存储多个指令先前遇到的操作数存储比较危险。

8. 发明申请

US20060259530A1 DECIMAL MULTIPLICATION FOR SUPERSCALER PROCESSORS 失效
标题翻译：超级处理器的十进制多路复用
公开(公告)号：US20060259530A1
公开(公告)日：2006-11-16
申请号：US11460296
申请日：2006-07-27
申请人： Fadi Busaba , Steven Carlough , Christopher Krygowski , John Rell
发明人： Fadi Busaba , Steven Carlough , Christopher Krygowski , John Rell
IPC分类号： G06F7/38
CPC分类号： G06F9/3001 , G06F7/496
摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.
摘要翻译：一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

9. 发明授权

US08464030B2 Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits 有权
标题翻译：基于指令字段，索引字段，操作数字段和各种其他指令文本位的指令破解和问题缩短
公开(公告)号：US08464030B2
公开(公告)日：2013-06-11
申请号：US12757330
申请日：2010-04-09
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Bruce Giamei , David Hutton
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Bruce Giamei , David Hutton
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3017 , G06F9/30032 , G06F9/30054 , G06F9/30058
摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.
摘要翻译：一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。至少接收一条指令。至少对指令进行分析。识别与该至少一条指令相关联的指令类型。分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。然后执行一组操作单元。

10. 发明申请

US20070214205A1 MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
标题翻译：用于可变宽度的签名和不相关操作的模块化二进制多路复用器
公开(公告)号：US20070214205A1
公开(公告)日：2007-09-13
申请号：US11749239
申请日：2007-05-16
申请人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
发明人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
摘要翻译：在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

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