专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090210662A1 MICROPROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR DIRECT PAGE PREFETCH IN MILLICODE CAPABLE COMPUTER SYSTEM 有权
标题翻译： MICROPROCESSOR，方法和计算机程序产品，用于在MILLICODE可编程计算机系统中直接提取
公开(公告)号：US20090210662A1
公开(公告)日：2009-08-20
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译：配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。提供了一种方法和计算机程序产品。

2. 发明授权

US08549255B2 Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权
标题翻译：微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取
公开(公告)号：US08549255B2
公开(公告)日：2013-10-01
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译：配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。提供了一种方法和计算机程序产品。

3. 发明授权

US07966474B2 System, method and computer program product for translating storage elements 有权
标题翻译：用于翻译存储元件的系统，方法和计算机程序产品
公开(公告)号：US07966474B2
公开(公告)日：2011-06-21
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/26
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

4. 发明申请

US20090217009A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING STORAGE ELEMENTS 有权
标题翻译：用于转储储存元件的系统，方法和计算机程序产品
公开(公告)号：US20090217009A1
公开(公告)日：2009-08-27
申请号：US12036520
申请日：2008-02-25
申请人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Bernd Nerz , David A. Schroter , Charles F. Webb
IPC分类号： G06F9/318
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30101 , G06F9/355
摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.
摘要翻译：一种用于计算机系统中的翻译的系统，方法和计算机程序产品。该系统包括包含地址转换表的基地址的通用寄存器。该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

5. 发明授权

US08112174B2 Processor, method and computer program product for fast selective invalidation of translation lookaside buffer 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性地无效翻译后备缓冲区
公开(公告)号：US08112174B2
公开(公告)日：2012-02-07
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

6. 发明授权

US06865645B1 Program store compare handling between instruction and operand caches 有权
标题翻译：程序存储在指令和操作数缓存之间的比较处理
公开(公告)号：US06865645B1
公开(公告)日：2005-03-08
申请号：US09677527
申请日：2000-10-02
申请人： Chung-Lung Kevin Shum , Dean G. Bair , Charles F. Webb , Mark A. Check , John S. Liptay
发明人： Chung-Lung Kevin Shum , Dean G. Bair , Charles F. Webb , Mark A. Check , John S. Liptay
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0848
摘要： A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
摘要翻译：一种支持包括使用包括执行单元的中央处理单元来修改多处理器系统中的后续指令的指令的程序的方法，以及指令单元和包括单独指令和操作数高速缓存的多个高速缓存。

7. 发明申请

US20090216994A1 PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性翻译翻译书写缓冲区
公开(公告)号：US20090216994A1
公开(公告)日：2009-08-27
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

8. 发明授权

US08032709B2 System, method and computer program product for handling shared cache lines in a multi-processor environment 失效
标题翻译：用于在多处理器环境中处理共享缓存行的系统，方法和计算机程序产品
公开(公告)号：US08032709B2
公开(公告)日：2011-10-04
申请号：US12035668
申请日：2008-02-22
申请人： Chung-Lung Kevin Shum , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3851 , G06F12/0815
摘要： A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.
摘要翻译：提供了一种用于处理共享高速缓存行以允许处理器在多处理器环境中的前进进行的系统，方法和计算机程序产品。为多处理器环境的处理器提供计数器和阈值，使得计数器对于跟随指令完成的每个排他交叉询问（XI）拒绝而增加，并且在独占XI确认上复位。如果XI拒绝计数器达到预设阈值，则通过阻止指令发出和预取尝试来消除处理器的流水线，从另一个处理器创建独占XI的窗口，在此之后恢复正常指令处理。将预设阈值配置为可编程值允许微调系统性能。

9. 发明授权

US07971034B2 Reduced overhead address mode change management in a pipelined, recycling microprocessor 失效
标题翻译：在流水线回收微处理器中减少开销地址模式更改管理
公开(公告)号：US07971034B2
公开(公告)日：2011-06-28
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

10. 发明授权

US07953932B2 System and method for avoiding deadlocks when performing storage updates in a multi-processor environment 有权
标题翻译：用于在多处理器环境中执行存储更新时避免死锁的系统和方法
公开(公告)号：US07953932B2
公开(公告)日：2011-05-31
申请号：US12030627
申请日：2008-02-13
申请人： Chung-Lung Kevin Shum , Brian D. Barrick , Aaron Tsai , Charles F. Webb
发明人： Chung-Lung Kevin Shum , Brian D. Barrick , Aaron Tsai , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F9/3824 , G06F9/3834 , G06F9/3867
摘要： A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion.
摘要翻译：一种用于在多处理器环境中执行存储更新时避免死锁的系统和方法。该系统包括具有本地高速缓存的处理器，具有临时缓冲器的存储队列，该临时缓冲器具有拒绝排他交叉询问（XI）的能力，同时询问的高速缓存行被独占地存储并被存储，以及用于执行方法的机制。该方法包括将处理器设置为慢速模式。接收包括具有一个或多个目标线的数据存储器的当前指令。执行当前指令，执行包括将与数据存储相关联的结果存储到临时缓冲器中。防止存储队列拒绝与当前指令的目标行相对应的排他的XI。每个目标行被采集为具有独占所有权的状态，并且在指令完成之后将来自临时缓冲器的内容写入每个目标行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式