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1. 发明授权

US07001783B2 Mask schemes for patterning magnetic tunnel junctions 失效
标题翻译：用于图案化磁隧道结的掩模方案
公开(公告)号：US07001783B2
公开(公告)日：2006-02-21
申请号：US10868328
申请日：2004-06-15
申请人： Gregory Costrini , Frank Findeis , Gill Yong Lee , Chanro Park
发明人： Gregory Costrini , Frank Findeis , Gill Yong Lee , Chanro Park
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
摘要翻译：磁记录装置的磁隧道结（MTJ）的图案化方法，可避免在刻蚀过程中将磁存储单元短路到上层的导线。一种方法包括使用具有两个材料层的硬掩模来图案化MTJ的下部磁性材料层。硬掩模的第一种材料是薄的并且包括耐蚀刻材料。沉积在第一材料上的硬掩模的第二材料比第一材料更厚并且耐蚀刻性更差。在下磁性材料层的蚀刻过程期间，至少部分第二材料被牺牲地去除。可以使用保形或非保形材料作为硬掩模的第二材料。用于图形MTJ的较低磁性材料的硬掩模可以包括单层非保形材料。

2. 发明申请

US20050277207A1 MASK SCHEMES FOR PATTERNING MAGNETIC TUNNEL JUNCTIONS 失效
标题翻译：用于绘制磁性隧道结的掩蔽方案
公开(公告)号：US20050277207A1
公开(公告)日：2005-12-15
申请号：US10868328
申请日：2004-06-15
申请人： Gregory Costrini , Frank Findeis , Gill Lee , Chanro Park
发明人： Gregory Costrini , Frank Findeis , Gill Lee , Chanro Park
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/22 , H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
摘要翻译：磁记录装置的磁隧道结（MTJ）的图案化方法，可避免在刻蚀过程中将磁存储单元短路到上层的导线。一种方法包括使用具有两个材料层的硬掩模来图案化MTJ的下部磁性材料层。硬掩模的第一种材料是薄的并且包括耐蚀刻材料。沉积在第一材料上的硬掩模的第二材料比第一材料更厚并且耐蚀刻性更差。在下磁性材料层的蚀刻过程期间，至少部分第二材料被牺牲地去除。可以使用保形或非保形材料作为硬掩模的第二材料。用于图形MTJ的较低磁性材料的硬掩模可以包括单层非保形材料。

3. 发明授权

US06812141B1 Recessed metal lines for protective enclosure in integrated circuits 失效
标题翻译：集成电路中用于保护外壳的嵌入式金属线
公开(公告)号：US06812141B1
公开(公告)日：2004-11-02
申请号：US10610609
申请日：2003-07-01
申请人： Michael C. Gaidis , Joachim Nuetzel , Walter Glashauser , Eugene O'Sullivan , Gregory Costrini , Stephen L. Brown , Frank Findeis , Chanro Park
发明人： Michael C. Gaidis , Joachim Nuetzel , Walter Glashauser , Eugene O'Sullivan , Gregory Costrini , Stephen L. Brown , Frank Findeis , Chanro Park
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L23/5226 , H01L23/53238 , H01L27/222 , H01L2924/0002 , H01L2924/00
摘要： Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.
摘要翻译：衬垫材料如钽，氮化钽，碳化硅中的金属化的封装区域允许使用侵蚀性或苛刻的加工步骤。这些突出的处理步骤提供了制造新器件架构的可能性。此外，通过封装金属化区域，可以防止金属离子迁移和电迁移。此外，金属化的封装区域可以用作自对准蚀刻掩模。因此，蚀刻在相邻的金属化区域之间的通孔允许分配给通孔的衬底的面积被显着地减小，而不增加相邻金属化区域的电短路的可能性。

4. 发明授权

US06849465B2 Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition 失效
标题翻译：在磁堆叠沉积之前图案化磁存储单元底电极的方法
公开(公告)号：US06849465B2
公开(公告)日：2005-02-01
申请号：US10600920
申请日：2003-06-20
申请人： Chanro Park , Gill Yong Lee
发明人： Chanro Park , Gill Yong Lee
IPC分类号： H01F10/00 , H01L21/00 , H01L21/3213 , H01L27/22 , H01L43/12
CPC分类号： H01L43/12
摘要： A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.
摘要翻译：图案化用于磁存储单元的底电极的方法。在沉积磁隧道结（MTJ）材料层的软层之前，将底部电极图案化，从而防止在软层的侧壁上形成栅栏，这可能导致随后形成的磁记录的导线的短路设备。牺牲掩模用于对底部电极材料进行图案化，并且在底部电极材料的图案化期间消耗或去除牺牲掩模的至少一部分。然后使用硬掩模沉积和图案化软层。

5. 发明授权

US08871635B2 Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate 有权
标题翻译：用于形成在衬底内具有嵌入式电互连的集成电路的集成电路和工艺
公开(公告)号：US08871635B2
公开(公告)日：2014-10-28
申请号：US13466895
申请日：2012-05-08
申请人： Chanro Park , Errol T. Ryan
发明人： Chanro Park , Errol T. Ryan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76883 , H01L21/76832 , H01L21/76834
摘要： Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.
摘要翻译：提供了用于形成集成电路的集成电路和工艺。用于形成集成电路的示例性方法包括提供包括氧化物层和设置在氧化物层上的保护层的衬底。通过保护层蚀刻凹陷，并且至少部分地蚀刻到氧化物层中。阻挡材料沉积在凹部中以在氧化物层和凹部中的保护层之上形成阻挡层。导电材料沉积在凹槽中的势垒层上以形成嵌入的电互连。嵌入的电互连和阻挡层分别凹陷到衬底内的互连凹槽深度和阻挡凹槽深度。在使阻挡层凹陷之后，保护层的至少一部分保留在氧化物层上方，并且在凹陷阻挡层之后被去除。

6. 发明授权

US08791014B2 Methods of forming copper-based conductive structures on semiconductor devices 有权
标题翻译：在半导体器件上形成铜基导电结构的方法
公开(公告)号：US08791014B2
公开(公告)日：2014-07-29
申请号：US13422439
申请日：2012-03-16
申请人： Xunyuan Zhang , Hoon Kim , Chanro Park
发明人： Xunyuan Zhang , Hoon Kim , Chanro Park
IPC分类号： H01L21/768
CPC分类号： H01L21/76879 , H01L21/28556 , H01L21/28562 , H01L21/31144 , H01L21/32134 , H01L21/76805 , H01L21/76816
摘要： Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.
摘要翻译：本文公开了在诸如晶体管的半导体器件上形成铜基导电结构的各种方法。在一个示例中，该方法包括通过图案化的金属硬掩模层执行第一蚀刻工艺以限定绝缘材料层中的开口，通过绝缘材料层中的开口执行第二蚀刻工艺，该开口暴露一部分下面的含铜结构，进行湿蚀刻处理以去除图案化的金属硬掩模层，通过绝缘材料层中的开口进行选择性金属沉积工艺，以选择性地在含铜结构上形成金属区域，之后形成金属区域，在金属区域上方的开口中形成含铜结构体。

7. 发明授权

US08853069B2 Field effect transistor and method of fabrication 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08853069B2
公开(公告)日：2014-10-07
申请号：US13607954
申请日：2012-09-10
申请人： Hoon Kim , Kisik Choi , Chanro Park
发明人： Hoon Kim , Kisik Choi , Chanro Park
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/28 , H01L29/49 , H01L29/78 , H01L29/66 , H01L29/51
CPC分类号： H01L29/4966 , H01L21/28008 , H01L21/28088 , H01L21/28194 , H01L29/4236 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.
摘要翻译：公开了一种改进的场效应晶体管及其制造方法。在栅腔的基底和侧壁中形成阻挡层堆叠。阻挡层堆叠具有第一金属层和第二金属层。栅极电极金属沉积在空腔中。阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

8. 发明授权

US08432020B2 Capacitors, systems, and methods 失效
标题翻译：电容器，系统和方法
公开(公告)号：US08432020B2
公开(公告)日：2013-04-30
申请号：US12794251
申请日：2010-06-04
申请人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
发明人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L28/65
摘要： Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.
摘要翻译：公开了电容器，系统和方法。在一个实施例中，电容器包括第一电极。电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。电容器还可以包括具有邻近第一绝缘体层的负VCC的第二绝缘体层。电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。电容器还可以包括与第三绝缘体层相邻的第二电极。

9. 发明申请

US20100032642A1 Method of Manufacturing a Resistivity Changing Memory Cell, Resistivity Changing Memory Cell, Integrated Circuit, and Memory Module 审中-公开
标题翻译：制造电阻率变化记忆单元，电阻率变化存储单元，集成电路和存储器模块的方法
公开(公告)号：US20100032642A1
公开(公告)日：2010-02-11
申请号：US12187258
申请日：2008-08-06
申请人： Chanro Park , Rainer Leuschner
发明人： Chanro Park , Rainer Leuschner
IPC分类号： H01L21/283 , H01L45/00
CPC分类号： H01L27/24 , G11C11/161 , G11C13/0004 , G11C13/0011 , G11C2213/35 , G11C2213/71 , G11C2213/79 , H01L27/222 , H01L27/2436 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1266 , H01L45/149 , H01L45/1625 , H01L45/1675
摘要： According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask.
摘要翻译：根据实施例，提供一种制造包括多个电阻率变化存储单元的集成电路的方法。该方法包括：按顺序堆叠形成包括电阻率变化层，第一导电层，第二导电层和图案化掩模层的层叠层; 使用掩模层将第二导电层图案化为图案掩模; 使用第二导电层图案化第一导电层作为图案掩模; 以及使用第一导电层作为图案化掩模来构图电阻率变化层。

10. 发明申请

US20080273375A1 INTEGRATED CIRCUIT HAVING A MAGNETIC DEVICE 审中-公开
标题翻译：具有磁性装置的集成电路
公开(公告)号：US20080273375A1
公开(公告)日：2008-11-06
申请号：US11743449
申请日：2007-05-02
申请人： Faiz Dahmani , Chanro Park , Rainer Leuschner
发明人： Faiz Dahmani , Chanro Park , Rainer Leuschner
IPC分类号： H01L29/82 , G11C11/00 , H01L21/00
CPC分类号： G11C11/16 , B82Y25/00 , B82Y40/00 , G11B5/3903 , G11C11/1675 , H01F10/3254 , H01F10/3268 , H01F10/3272 , H01F41/302 , H01L43/08
摘要： An integrated circuit having a magnetic device is disclosed. In one embodiment, the integrated circuit includes a reference structure having a first blocking temperature. A storage structure is provided made of a ferromagnetic material. An antiferromagnetic structure is provided having a second blocking temperature lower than the first blocking temperature.
摘要翻译：公开了一种具有磁性装置的集成电路。在一个实施例中，集成电路包括具有第一阻挡温度的参考结构。存储结构由铁磁材料制成。提供具有低于第一阻塞温度的第二阻塞温度的反铁磁结构。

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