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1. 发明授权

US07001783B2 Mask schemes for patterning magnetic tunnel junctions 失效
标题翻译：用于图案化磁隧道结的掩模方案
公开(公告)号：US07001783B2
公开(公告)日：2006-02-21
申请号：US10868328
申请日：2004-06-15
申请人： Gregory Costrini , Frank Findeis , Gill Yong Lee , Chanro Park
发明人： Gregory Costrini , Frank Findeis , Gill Yong Lee , Chanro Park
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
摘要翻译：磁记录装置的磁隧道结（MTJ）的图案化方法，可避免在刻蚀过程中将磁存储单元短路到上层的导线。一种方法包括使用具有两个材料层的硬掩模来图案化MTJ的下部磁性材料层。硬掩模的第一种材料是薄的并且包括耐蚀刻材料。沉积在第一材料上的硬掩模的第二材料比第一材料更厚并且耐蚀刻性更差。在下磁性材料层的蚀刻过程期间，至少部分第二材料被牺牲地去除。可以使用保形或非保形材料作为硬掩模的第二材料。用于图形MTJ的较低磁性材料的硬掩模可以包括单层非保形材料。

2. 发明授权

US06849465B2 Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition 失效
标题翻译：在磁堆叠沉积之前图案化磁存储单元底电极的方法
公开(公告)号：US06849465B2
公开(公告)日：2005-02-01
申请号：US10600920
申请日：2003-06-20
申请人： Chanro Park , Gill Yong Lee
发明人： Chanro Park , Gill Yong Lee
IPC分类号： H01F10/00 , H01L21/00 , H01L21/3213 , H01L27/22 , H01L43/12
CPC分类号： H01L43/12
摘要： A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.
摘要翻译：图案化用于磁存储单元的底电极的方法。在沉积磁隧道结（MTJ）材料层的软层之前，将底部电极图案化，从而防止在软层的侧壁上形成栅栏，这可能导致随后形成的磁记录的导线的短路设备。牺牲掩模用于对底部电极材料进行图案化，并且在底部电极材料的图案化期间消耗或去除牺牲掩模的至少一部分。然后使用硬掩模沉积和图案化软层。

3. 发明授权

US07682841B2 Method of forming integrated circuit having a magnetic tunnel junction device 有权
标题翻译：形成具有磁性隧道结装置的集成电路的方法
公开(公告)号：US07682841B2
公开(公告)日：2010-03-23
申请号：US11743497
申请日：2007-05-02
申请人： Faiz Dahmani , Gill Yong Lee
发明人： Faiz Dahmani , Gill Yong Lee
IPC分类号： H01L21/00
CPC分类号： H01F41/302 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/3254 , H01F10/3272 , H01F10/3295 , H01L43/12 , Y10S438/905
摘要： A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.
摘要翻译：公开了一种具有磁性隧道结装置的集成电路的制造方法。该方法包括在底部导电结构上方沉积底部钉扎结构。第一铁磁结构沉积在腔室中的底部钉扎结构上方。在腔室中的第一铁磁层结构上方沉积隧道势垒结构，并且在另一个室中的磁性隧道结装置的隧道势垒结构上方沉积第二铁磁结构。

4. 发明申请

US20090072348A1 Integrated Circuits; Methods for Manufacturing an Integrated Circuit and Memory Module 审中-公开
标题翻译：集成电路; 制造集成电路和存储器模块的方法
公开(公告)号：US20090072348A1
公开(公告)日：2009-03-19
申请号：US11857703
申请日：2007-09-19
申请人： Ulrich Klostermann , Gill Yong Lee
发明人： Ulrich Klostermann , Gill Yong Lee
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： H01L45/1658 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/145
摘要： Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate, at least one first electrode disposed in or above the substrate, ion conductor doping material disposed above the at least one first electrode, ion conductor material disposed above the ion conductor doping material, and at least one second electrode disposed above the ion conductor material.
摘要翻译：本发明的实施例一般涉及集成电路，制造集成电路和存储器模块的方法。在本发明的实施例中，提供具有可编程布置的集成电路。可编程布置包括基板，设置在基板中或上方的至少一个第一电极，设置在至少一个第一电极上方的离子导体掺杂材料，设置在离子导体掺杂材料上方的离子导体材料，以及设置在离子导体掺杂材料上的至少一个第二电极高于离子导体材料。

5. 发明授权

US06300672B1 Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication 失效
标题翻译：用于氟化硅玻璃膜的氮氧化硅帽在金属间电介质半导体制造中
公开(公告)号：US06300672B1
公开(公告)日：2001-10-09
申请号：US09120630
申请日：1998-07-22
申请人： Gill Yong Lee
发明人： Gill Yong Lee
IPC分类号： H01L2358
CPC分类号： H01L21/02131 , H01L21/0214 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/3145 , H01L21/31629 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/3192 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by a single dry etching step, to expose pattern portions of the conductive layer for metallization. Upon metallization, the substrate is provided with a combination of the FSG layer and silicon oxynitride layer, in which the silicon oxynitride layer prevents fluorine substance outflow therethrough from the underlying FSG layer to an overlying conductive layer.
摘要翻译：提供半导体器件和在半导体衬底上形成图案化导电层的方法，以防止氟物质从其上的氟化硅酸盐玻璃（FSG）层流出，并同时抑制光波反射到光致抗蚀剂层中光刻处理。依次用导电层，电介质（例如，二氧化硅）衬垫，FSG层，氮氧化硅层涂覆衬底，防止氟物质从FSG层流出并形成抗反射涂层（ARC），以及光致抗蚀剂层。光致抗蚀剂层被曝光和显影以露出下面的氮氧化硅层的图案部分。然后例如通过单次干蚀刻步骤去除氮氧化硅ARC层的未覆盖图案部分和FSG层和电介质衬垫的相应的下部，以暴露用于金属化的导电层的图案部分。在金属化时，基板设置有FSG层和氮氧化硅层的组合，其中氧氮化硅层防止氟物质从下面的FSG层流出到上覆的导电层。

6. 发明申请

US20080253168A1 Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuit 有权
标题翻译：集成电路，电阻率变化存储器件，存储器模块和制造集成电路的方法
公开(公告)号：US20080253168A1
公开(公告)日：2008-10-16
申请号：US11787143
申请日：2007-04-13
申请人： Philippe Blanchard , Gill Yong Lee
发明人： Philippe Blanchard , Gill Yong Lee
IPC分类号： G11C11/00 , H01R43/00
CPC分类号： H01L27/24 , H01L27/2463 , H01L45/085 , H01L45/12 , H01L45/1233 , Y10T29/49117
摘要： According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite structure, the protection layer protecting the electrode layer against electromagnetic waves.
摘要翻译：根据本发明的一个实施例，存储器件包括复合结构，其包括电阻率变化层和布置在电阻率变化层上或上的电极层。电阻率变化存储装置还包括布置在复合结构上或上方的保护层，保护层保护电极层抵抗电磁波。

7. 发明授权

US07075807B2 Magnetic memory with static magnetic offset field 失效
标题翻译：具有静磁场的磁记忆体
公开(公告)号：US07075807B2
公开(公告)日：2006-07-11
申请号：US10920562
申请日：2004-08-18
申请人： Rainer Leuschner , Daniel Braun , Gill Yong Lee , Ulrich Klostermann
发明人： Rainer Leuschner , Daniel Braun , Gill Yong Lee , Ulrich Klostermann
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/16 , H01L43/08
摘要： A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
摘要翻译：磁阻或磁存储元件和具有一个或多个磁存储元件的磁随机存取存储器。存储元件包括包含第一和第二磁性层的磁性隧道结。第一磁性层具有自由磁化。第一磁性层的自由磁化磁耦合到第一电流线和用于切换自由磁化的第二电流线，以及用于在第一和第二电流中的至少一个方向上施加静态磁偏移场的机构线条。

8. 发明授权

US06281084B1 Disposable spacers for improved array gapfill in high density DRAMs 失效
标题翻译：一次性间隔物，用于改善高密度DRAM中的阵列间隙填充
公开(公告)号：US06281084B1
公开(公告)日：2001-08-28
申请号：US09386832
申请日：1999-08-31
申请人： Hiroyuki Akatsu , Ramachandra Divakaruni , Gill Yong Lee
发明人： Hiroyuki Akatsu , Ramachandra Divakaruni , Gill Yong Lee
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/76897 , H01L27/10873 , H01L27/10894
摘要： There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.
摘要翻译：公开了形成用于半导体器件的栅极导体的工艺。该方法开始于提供其上形成有栅极堆叠的半导体衬底的步骤，栅叠层包括侧壁。电介质间隔物形成在栅极导体侧壁上，电介质间隔物包括内部间隔物和外部间隔物，外部间隔物是掺杂的玻璃材料。离子在介质间隔物的外侧注入到半导体衬底中。然后拆下外隔离物。

9. 发明申请

US20090218644A1 Integrated Circuit, Memory Device, and Method of Manufacturing an Integrated Circuit 审中-公开
标题翻译：集成电路，存储器件和制造集成电路的方法
公开(公告)号：US20090218644A1
公开(公告)日：2009-09-03
申请号：US12040035
申请日：2008-02-29
申请人： Gill Yong Lee
发明人： Gill Yong Lee
IPC分类号： H01L29/82 , H01L23/52 , H01L21/822
CPC分类号： H01L23/53238 , B82Y10/00 , G11C5/02 , G11C5/063 , G11C11/15 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C2213/18 , G11C2213/71 , H01L23/5329 , H01L27/222 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of conductive lines is provided. The conductive lines are configured to guide electric currents or voltages. The conductive lines are at least partially surrounded by material which increases the electric field confinement of electric fields occurring within the conductive lines, and which functions as a diffusion barrier for material included within the conductive lines.
摘要翻译：根据本发明的一个实施例，提供了包括多条导线的集成电路。导线被配置成引导电流或电压。导电线至少部分地由导电线内发生的电场的电场限制的材料包围，并且其作为包含在导电线内的材料的扩散阻挡层起作用。

10. 发明申请

US20080274567A1 METHOD OF FORMING INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE 有权
标题翻译：形成具有磁性隧道连接装置的集成电路的方法
公开(公告)号：US20080274567A1
公开(公告)日：2008-11-06
申请号：US11743497
申请日：2007-05-02
申请人： Faiz Dahmani , Gill Yong Lee
发明人： Faiz Dahmani , Gill Yong Lee
IPC分类号： H01L21/00 , H01F10/00
CPC分类号： H01F41/302 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/3254 , H01F10/3272 , H01F10/3295 , H01L43/12 , Y10S438/905
摘要： A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.
摘要翻译：公开了一种具有磁性隧道结装置的集成电路的制造方法。该方法包括在底部导电结构上方沉积底部钉扎结构。第一铁磁结构沉积在腔室中的底部钉扎结构上方。在腔室中的第一铁磁层结构上方沉积隧道势垒结构，并且在另一个室中的磁性隧道结装置的隧道势垒结构上方沉积第二铁磁结构。

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