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1. 发明申请

US20130299922A1 INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE 有权
标题翻译：集成电路及其替代盖结构的方法
公开(公告)号：US20130299922A1
公开(公告)日：2013-11-14
申请号：US13467659
申请日：2012-05-09
申请人： Kisik Choi , Hoon Kim
发明人： Kisik Choi , Hoon Kim
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/823462 , H01L21/823475 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit includes depositing a layer of a high-k dielectric material; depositing a layer of a work function shifter material over a portion of the high-k dielectric material to form an overlapping region; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material to as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric and work function shifter materials in the overlapping region; and depositing a layer of a first replacement gate fill material to obtain multiple threshold voltages.
摘要翻译：本文提供了集成电路和制造集成电路的方法。在一个实施例中，制造集成电路的方法包括沉积高k电介质材料层; 在所述高k电介质材料的一部分上沉积一层功函子移位器材料以形成重叠区域; 热处理高k电介质材料层和功函数换向器材料层，以便通过热扩散形成转换介电材料，热扩散是高k电介质和功能转换材料在重叠区域中的组合 ; 以及沉积一层第一替代栅极填充材料以获得多个阈值电压。

2. 发明授权

US08354719B2 Finned semiconductor device with oxygen diffusion barrier regions, and related fabrication methods 有权
标题翻译：具有氧扩散阻挡区域的翅片半导体器件及相关制造方法
公开(公告)号：US08354719B2
公开(公告)日：2013-01-15
申请号：US12708213
申请日：2010-02-18
申请人： Kisik Choi , Robert J. Miller
发明人： Kisik Choi , Robert J. Miller
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L21/76229 , H01L29/66545 , H01L29/785
摘要： A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure.
摘要翻译：提供半导体器件及相关的制造方法。一种示例性的制造方法形成覆盖氧化物层的翅片布置，其中翅片布置包括一个或多个半导体翅片结构。该方法通过氮化氧化物层的暴露部分而不渗透一个或多个半导体鳍结构，导致氧化物层的氮化部分继续。此后，栅极结构横向地形成在翅片布置上，并且覆盖在氧化物层的暴露部分上。氧化物层的氮化部分基本上抑制氧从氧化物层扩散到栅极结构中。

3. 发明申请

US20120052666A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING COMPRESSIVE MATERIAL WITH A REPLACEMENT GATE TECHNIQUE 有权
标题翻译：使用具有替代门技术的压缩材料制造半导体器件的方法
公开(公告)号：US20120052666A1
公开(公告)日：2012-03-01
申请号：US12869341
申请日：2010-08-26
申请人： Kisik CHOI
发明人： Kisik CHOI
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/76801 , H01L21/76829 , H01L29/7843
摘要： The disclosed method of fabricating a semiconductor device structure forms a dummy gate structure on a substrate, deposits a dielectric material overlying the dummy gate structure in a manner that forms angled sidewalls of the deposited dielectric material outboard the spacers, and conformally deposits a compressive material overlying the deposited dielectric material such that the deposited compressive material forms angled peaks overlying the dummy gate structure. The method continues by forming an upper dielectric layer overlying the deposited compressive material, planarizing the resulting device structure, and exposing the temporary gate element of the dummy gate structure. Thereafter, the temporary gate element is removed, while leaving sections of the deposited compressive material outboard the spacers, and the gate recess is filled with a gate electrode material. The compressive material pulls the upper ends of the spacers apart to facilitate filling the gate recess.
摘要翻译：所公开的制造半导体器件结构的方法在衬底上形成虚拟栅极结构，以覆盖虚拟栅极结构的方式沉积介电材料，其方式是在隔离物外侧形成沉积的介电材料的成角度的侧壁，并且共形地沉积覆盖的压缩材料沉积的介电材料使得沉积的压缩材料形成覆盖在虚拟栅极结构上的倾斜峰值。该方法通过形成覆盖沉积的压缩材料的上介电层，平坦化所得到的器件结构，以及暴露伪栅极结构的临时栅极元件来继续。此后，移除临时栅极元件，同时将沉积的压缩材料的部分留在隔板上，并且栅极凹槽填充有栅电极材料。压缩材料将间隔物的上端拉开以便于填充浇口凹槽。

4. 发明申请

US20110198696A1 FINNED SEMICONDUCTOR DEVICE WITH OXYGEN DIFFUSION BARRIER REGIONS, AND RELATED FABRICATION METHODS 有权
标题翻译：具有氧扩散障碍区域的精细半导体器件及相关制造方法
公开(公告)号：US20110198696A1
公开(公告)日：2011-08-18
申请号：US12708213
申请日：2010-02-18
申请人： Kisik CHOI , Robert J. Miller
发明人： Kisik CHOI , Robert J. Miller
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/66795 , H01L21/76229 , H01L29/66545 , H01L29/785
摘要： A semiconductor device and related fabrication methods are provided. One exemplary fabrication method forms a fin arrangement overlying an oxide layer, where the fin arrangement includes one or more semiconductor fin structures. The method continues by nitriding exposed portions of the oxide layer without nitriding the one or more semiconductor fin structures, resulting in nitrided portions of the oxide layer. Thereafter, a gate structure is formed transversely overlying the fin arrangement, and overlying the exposed portions of the oxide layer. The nitrided portions of the oxide layer substantially inhibit diffusion of oxygen from the oxide layer into the gate structure.
摘要翻译：提供半导体器件及相关的制造方法。一种示例性的制造方法形成覆盖氧化物层的翅片布置，其中翅片布置包括一个或多个半导体翅片结构。该方法通过氮化氧化物层的暴露部分而不渗透一个或多个半导体鳍结构，导致氧化物层的氮化部分继续。此后，栅极结构横向地形成在翅片布置上，并且覆盖在氧化物层的暴露部分上。氧化物层的氮化部分基本上抑制氧从氧化物层扩散到栅极结构中。

5. 发明申请

US20140070283A1 FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION 有权
标题翻译：场效应晶体管和制造方法
公开(公告)号：US20140070283A1
公开(公告)日：2014-03-13
申请号：US13607954
申请日：2012-09-10
申请人： Hoon Kim , Kisik Choi , Chanro Park
发明人： Hoon Kim , Kisik Choi , Chanro Park
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28008 , H01L21/28088 , H01L21/28194 , H01L29/4236 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.
摘要翻译：公开了一种改进的场效应晶体管及其制造方法。在栅腔的基底和侧壁中形成阻挡层堆叠。阻挡层堆叠具有第一金属层和第二金属层。栅极电极金属沉积在空腔中。阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

6. 发明申请

US20130270646A1 INTEGRATED CIRCUITS HAVING IMPROVED METAL GATE STRUCTURES AND METHODS FOR FABRICATING SAME 有权
标题翻译：具有改进的金属结构结构的集成电路及其制造方法
公开(公告)号：US20130270646A1
公开(公告)日：2013-10-17
申请号：US13445719
申请日：2012-04-12
申请人： Hoon Kim , Kisik Choi
发明人： Hoon Kim , Kisik Choi
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L29/66545 , H01L21/823842 , H01L29/4966
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，制造集成电路的方法包括在半导体表面上的层间绝缘材料的NFET区域中的PFET区域中形成PFET沟槽和NFET沟槽。 NFET沟槽部分地填充有N型功函数金属层以限定内腔。 NFET沟槽中的PFET沟槽和内腔部分地填充有P型功函数金属层，以在每个沟槽中限定中心空隙。在该方法中，中心空隙填充有金属填充物以形成金属栅极结构。然后执行单个凹陷处理以在每个沟槽内凹入每个金属栅极结构的部分，以在相应的金属栅极结构上方的每个沟槽中形成凹陷。

7. 发明授权

US08420470B2 Method of fabricating a semiconductor device using compressive material with a replacement gate technique 有权
标题翻译：使用替代栅极技术制造使用压缩材料的半导体器件的方法
公开(公告)号：US08420470B2
公开(公告)日：2013-04-16
申请号：US12869341
申请日：2010-08-26
申请人： Kisik Choi
发明人： Kisik Choi
IPC分类号： H01L21/338 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/76801 , H01L21/76829 , H01L29/7843
摘要： The disclosed method of fabricating a semiconductor device structure forms a dummy gate structure on a substrate, deposits a dielectric material overlying the dummy gate structure in a manner that forms angled sidewalls of the deposited dielectric material outboard the spacers, and conformally deposits a compressive material overlying the deposited dielectric material such that the deposited compressive material forms angled peaks overlying the dummy gate structure. The method continues by forming an upper dielectric layer overlying the deposited compressive material, planarizing the resulting device structure, and exposing the temporary gate element of the dummy gate structure. Thereafter, the temporary gate element is removed, while leaving sections of the deposited compressive material outboard the spacers, and the gate recess is filled with a gate electrode material. The compressive material pulls the upper ends of the spacers apart to facilitate filling the gate recess.
摘要翻译：所公开的制造半导体器件结构的方法在衬底上形成虚拟栅极结构，以覆盖虚拟栅极结构的方式沉积介电材料，其方式是在隔离物外侧形成沉积的介电材料的成角度的侧壁，并且共形地沉积覆盖的压缩材料沉积的介电材料使得沉积的压缩材料形成覆盖在虚拟栅极结构上的倾斜峰值。该方法通过形成覆盖沉积的压缩材料的上介电层，平坦化所得到的器件结构，以及暴露伪栅极结构的临时栅极元件来继续。此后，移除临时栅极元件，同时将沉积的压缩材料的部分留在隔板上，并且栅极凹槽填充有栅电极材料。压缩材料将间隔物的上端拉开以便于填充浇口凹槽。

8. 发明授权

US08236686B2 Dual metal gates using one metal to alter work function of another metal 失效
标题翻译：双金属门使用一种金属来改变另一种金属的功能
公开(公告)号：US08236686B2
公开(公告)日：2012-08-07
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

9. 发明授权

US07332433B2 Methods of modulating the work functions of film layers 失效
标题翻译：调制膜层功能的方法
公开(公告)号：US07332433B2
公开(公告)日：2008-02-19
申请号：US11233356
申请日：2005-09-22
申请人： Kisik Choi , Husam Alshareef , Prashant Majhi
发明人： Kisik Choi , Husam Alshareef , Prashant Majhi
IPC分类号： H01R24/00
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques may be used to define the gate stack.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的具有不同功函数的两个金属栅极叠层的方法。第一金属层可沉积在栅极电介质上，随后沉积第二金属层，其中第二金属层调制第一金属层的功函数。第二金属层并随后蚀刻，暴露第一金属层的一部分。可以在蚀刻的第二金属层和暴露的第一金属层上沉积第三金属层，其中第三金属层可以调节暴露的第一金属层的功函数。可以使用随后的制造技术来定义栅极堆叠。

10. 发明授权

US08941184B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US08941184B2
公开(公告)日：2015-01-27
申请号：US13327870
申请日：2011-12-16
申请人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
摘要翻译：一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。还公开了制造半导体器件的方法，其包括栅极最后工艺。

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