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1. 发明申请

US20080274567A1 METHOD OF FORMING INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE 有权
标题翻译：形成具有磁性隧道连接装置的集成电路的方法
公开(公告)号：US20080274567A1
公开(公告)日：2008-11-06
申请号：US11743497
申请日：2007-05-02
申请人： Faiz Dahmani , Gill Yong Lee
发明人： Faiz Dahmani , Gill Yong Lee
IPC分类号： H01L21/00 , H01F10/00
CPC分类号： H01F41/302 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/3254 , H01F10/3272 , H01F10/3295 , H01L43/12 , Y10S438/905
摘要： A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.
摘要翻译：公开了一种具有磁性隧道结装置的集成电路的制造方法。该方法包括在底部导电结构上方沉积底部钉扎结构。第一铁磁结构沉积在腔室中的底部钉扎结构上方。在腔室中的第一铁磁层结构上方沉积隧道势垒结构，并且在另一个室中的磁性隧道结装置的隧道势垒结构上方沉积第二铁磁结构。

2. 发明申请

US20080217670A1 Methods of manufacturing a semiconductor device; method of manufacturing a memory cell; semiconductor device; semiconductor processing device; integrated circuit having a memory cell 有权
标题翻译：制造半导体器件的方法; 制造存储单元的方法; 半导体器件; 半导体处理装置; 集成电路具有存储单元
公开(公告)号：US20080217670A1
公开(公告)日：2008-09-11
申请号：US11714091
申请日：2007-03-05
申请人： Faiz Dahmani
发明人： Faiz Dahmani
IPC分类号： H01L27/108 , B05B5/00 , B23P19/00 , H01L29/12 , H01L21/00
CPC分类号： H01L45/1233 , H01L45/085 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/1625 , H01L45/1641 , H01L45/1658 , Y10T29/53204 , Y10T428/12528
摘要： Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.
摘要翻译：提供制造半导体器件的方法，制造存储单元的方法，半导体器件，半导体处理器件和存储器单元。在一个实施例中，提供一种制造半导体器件的方法，包括在提供金属期间至少部分地使用光照射形成金属掺杂的硫族化物层。

3. 发明申请

US20130126813A1 METHOD OF FABRICATING A MICROELECTRONIC DEVICE WITH PROGRAMMABLE MEMORY 有权
标题翻译：用可编程存储器制造微电子器件的方法
公开(公告)号：US20130126813A1
公开(公告)日：2013-05-23
申请号：US13539751
申请日：2012-07-02
申请人： Faiz Dahmani
发明人： Faiz Dahmani
IPC分类号： H01L45/00
CPC分类号： H01L45/1658 , C03C3/321 , C03C17/09 , C03C23/002 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/1625
摘要： A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device.
摘要翻译：提供了一种用于制造具有可编程存储器的微电子器件的方法，其包括：i）在第一电极上沉积具有硫族化物的材料的中间层; ii）用紫外线照射步骤i的中间层; iii）在步骤ii中获得的中间层上沉积可电离的金属层; iv）将来自步骤iii的可电离金属层的金属离子扩散到中间层中以形成含有金属离子的硫族化物材料; 和v）在步骤iv中获得的含有金属离子的硫族化物材料层上沉积第二电极以形成微电子器件。

4. 发明申请

US20080273375A1 INTEGRATED CIRCUIT HAVING A MAGNETIC DEVICE 审中-公开
标题翻译：具有磁性装置的集成电路
公开(公告)号：US20080273375A1
公开(公告)日：2008-11-06
申请号：US11743449
申请日：2007-05-02
申请人： Faiz Dahmani , Chanro Park , Rainer Leuschner
发明人： Faiz Dahmani , Chanro Park , Rainer Leuschner
IPC分类号： H01L29/82 , G11C11/00 , H01L21/00
CPC分类号： G11C11/16 , B82Y25/00 , B82Y40/00 , G11B5/3903 , G11C11/1675 , H01F10/3254 , H01F10/3268 , H01F10/3272 , H01F41/302 , H01L43/08
摘要： An integrated circuit having a magnetic device is disclosed. In one embodiment, the integrated circuit includes a reference structure having a first blocking temperature. A storage structure is provided made of a ferromagnetic material. An antiferromagnetic structure is provided having a second blocking temperature lower than the first blocking temperature.
摘要翻译：公开了一种具有磁性装置的集成电路。在一个实施例中，集成电路包括具有第一阻挡温度的参考结构。存储结构由铁磁材料制成。提供具有低于第一阻塞温度的第二阻塞温度的反铁磁结构。

5. 发明授权

US08501525B2 Method of fabrication of programmable memory microelectric device 有权
标题翻译：可编程存储器微电子器件的制造方法
公开(公告)号：US08501525B2
公开(公告)日：2013-08-06
申请号：US13150351
申请日：2011-06-01
申请人： Faiz Dahmani
发明人： Faiz Dahmani
IPC分类号： H01L21/00 , G11C11/24
CPC分类号： H01L45/085 , H01L45/141 , H01L45/142 , H01L45/1658
摘要： A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.
摘要翻译：制造可编程存储器微电子器件的方法包括在第一电极上沉积具有硫族化物的材料的中间层; 在中间层上沉积可电离的金属层; 用紫外线照射可电离金属层，使得可离子化金属层的金属离子扩散到中间层，形成含有金属离子的硫族化物材料，并在第一步中获得的含有金属离子的硫族化物材料层上沉积第二电极。第二和第三步骤重复至少n次，其中n是大于或等于1的整数。在第二步骤期间沉积的可离子化金属层具有足够小的厚度，使得在照射期间金属离子可能完全扩散（第三）步骤。

6. 发明授权

US08268664B2 Methods of manufacturing a semiconductor device; method of manufacturing a memory cell; semiconductor device; semiconductor processing device; integrated circuit having a memory cell 有权
标题翻译：制造半导体器件的方法; 制造存储单元的方法; 半导体器件; 半导体处理装置; 集成电路具有存储单元
公开(公告)号：US08268664B2
公开(公告)日：2012-09-18
申请号：US11714091
申请日：2007-03-05
申请人： Faiz Dahmani
发明人： Faiz Dahmani
IPC分类号： H01L21/00
CPC分类号： H01L45/1233 , H01L45/085 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/1625 , H01L45/1641 , H01L45/1658 , Y10T29/53204 , Y10T428/12528
摘要： Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.
摘要翻译：提供制造半导体器件的方法，制造存储单元的方法，半导体器件，半导体处理器件和存储器单元。在一个实施例中，提供一种制造半导体器件的方法，包括在提供金属期间至少部分地使用光照射形成金属掺杂的硫族化物层。

7. 发明申请

US20120073957A1 USE OF A PROCESS FOR DEPOSITION BY SPUTTERING OF A CHALCOGENIDE LAYER 审中-公开
标题翻译：使用通过溅射聚氯乙烯层沉积的方法
公开(公告)号：US20120073957A1
公开(公告)日：2012-03-29
申请号：US13246078
申请日：2011-09-27
申请人： Faiz Dahmani
发明人： Faiz Dahmani
IPC分类号： C23C14/34 , C23C14/06
CPC分类号： C23C14/0623 , C23C14/3414 , C23C14/548
摘要： A deposition process includes sputtering of a layer of a material having a chalcogenide compound, the chalcogenide being composed of at least one chalcogen on and at least one electropositive element, in order to increase or to decrease the atomic proportion (%) of the chalcogen ion with respect to the atomic proportion (%) of the electropositive element.
摘要翻译：沉积工艺包括溅射具有硫属化物化合物的材料层，硫属化物由至少一个硫族元素组成至少一个正电荷元素，以增加或降低硫属元素离子的原子比例（％）相对于正电性元素的原子比例（％）。

8. 发明申请

US20110297910A1 METHOD OF FABRICATION OF PROGRAMMABLE MEMORY MICROELECTRIC DEVICE 有权
标题翻译：可编程存储器微电子器件的制造方法
公开(公告)号：US20110297910A1
公开(公告)日：2011-12-08
申请号：US13150351
申请日：2011-06-01
申请人： Faiz Dahmani
发明人： Faiz Dahmani
IPC分类号： H01L21/62 , H01L45/00
CPC分类号： H01L45/085 , H01L45/141 , H01L45/142 , H01L45/1658
摘要： A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.
摘要翻译：一种制造可编程存储器微电子器件的方法包括：在第一电极上沉积具有硫族化物的材料的中间层; 在中间层上沉积可电离的金属层; 用紫外线照射可电离金属层，使得可离子化金属层的金属离子扩散到中间层，形成含有金属离子的硫族化物材料，并在第一步中获得的含有金属离子的硫族化物材料层上沉积第二电极。第二和第三步骤重复至少n次，其中n是大于或等于1的整数。在第二步骤期间沉积的可离子化金属层具有足够小的厚度，使得在照射期间金属离子可能完全扩散（第三）步骤。

9. 发明授权

US07682841B2 Method of forming integrated circuit having a magnetic tunnel junction device 有权
标题翻译：形成具有磁性隧道结装置的集成电路的方法
公开(公告)号：US07682841B2
公开(公告)日：2010-03-23
申请号：US11743497
申请日：2007-05-02
申请人： Faiz Dahmani , Gill Yong Lee
发明人： Faiz Dahmani , Gill Yong Lee
IPC分类号： H01L21/00
CPC分类号： H01F41/302 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/3254 , H01F10/3272 , H01F10/3295 , H01L43/12 , Y10S438/905
摘要： A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.
摘要翻译：公开了一种具有磁性隧道结装置的集成电路的制造方法。该方法包括在底部导电结构上方沉积底部钉扎结构。第一铁磁结构沉积在腔室中的底部钉扎结构上方。在腔室中的第一铁磁层结构上方沉积隧道势垒结构，并且在另一个室中的磁性隧道结装置的隧道势垒结构上方沉积第二铁磁结构。

10. 发明申请

US20090103351A1 Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module 审中-公开
标题翻译：集成电路，制造集成电路的方法和存储器模块
公开(公告)号：US20090103351A1
公开(公告)日：2009-04-23
申请号：US11877558
申请日：2007-10-23
申请人： Cay-Uwe Pinnow , Wolfgang Raberg , Faiz Dahmani
发明人： Cay-Uwe Pinnow , Wolfgang Raberg , Faiz Dahmani
IPC分类号： G11C11/24 , H01G9/00
CPC分类号： H01G9/025 , G11C13/0011 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01G9/15 , H01L27/24 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： According to one embodiment of the present invention, an integrated circuit includes at least one memory device including: a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer being disposed between the reactive electrode layer and the inert electrode layer; at least one interface layer being disposed between the solid electrolyte layer and the reactive electrode layer and/or between the solid electrolyte layer and the inert electrode layer. The material parameters of the at least one interface layer are chosen such that a crystallization of the solid electrolyte layer is at least partially suppressed.
摘要翻译：根据本发明的一个实施例，集成电路包括至少一个存储器件，包括：反应电极层，惰性电极层和固体电解质层，设置在反应电极层和惰性电极层之间; 至少一个界面层设置在固体电解质层和反应性电极层之间和/或固体电解质层和惰性电极层之间。选择至少一个界面层的材料参数，使得至少部分地抑制固体电解质层的结晶。

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