专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06887716B2 Process for producing high quality PZT films for ferroelectric memory integrated circuits 有权
标题翻译：用于生产用于铁电存储器集成电路的高品质PZT膜的工艺
公开(公告)号：US06887716B2
公开(公告)日：2005-05-03
申请号：US09742204
申请日：2000-12-20
申请人： Glen Fox , Fan Chu , Brian Eastep , Tomohiro Takamatsu , Yoshimasa Horii , Ko Nakamura
发明人： Glen Fox , Fan Chu , Brian Eastep , Tomohiro Takamatsu , Yoshimasa Horii , Ko Nakamura
IPC分类号： H01L27/105 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8246 , H01L21/00
CPC分类号： H01L28/56 , H01L21/02197 , H01L21/02266 , H01L21/31691 , Y10S438/957
摘要： A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.
摘要翻译：制造集成电路的铁电电容器元件的方法包括沉积优选由贵金属制成的导电底电极层的步骤。底部电极被一层铁电介质材料覆盖。在沉积包含贵金属氧化物的第二电极层之前，用第一退火对铁电介质进行退火。导电性顶电极层的沉积之后，用第二次退火退火铁电电介质材料层和上电极层。第一和第二退火通过快速热退火进行。

2. 发明授权

US06964873B2 Semiconductor device having a ferroelectric capacitor and a fabrication process thereof 失效
标题翻译：具有铁电电容器的半导体器件及其制造方法
公开(公告)号：US06964873B2
公开(公告)日：2005-11-15
申请号：US09551233
申请日：2000-04-17
申请人： Katsuyoshi Matsuura , Mari Tani , Yoshimasa Horii , Fan Chu , Glen R. Fox , Brian Eastep
发明人： Katsuyoshi Matsuura , Mari Tani , Yoshimasa Horii , Fan Chu , Glen R. Fox , Brian Eastep
IPC分类号： H01G4/12 , H01G4/33 , H01G4/40 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8246 , H01L27/105 , H01L21/00 , H01L21/8242
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/02266 , H01L21/31691 , H01L27/11507 , H01L28/55
摘要： A method of fabricating a semiconductor device having a ferroelectric capacitor includes the steps of forming a lower electrode layer of the ferroelectric capacitor on an insulation film covering an active device element, forming a ferroelectric film on the lower electrode layer as a capacitor insulation film, crystallizing the ferroelectric film by applying a thermal annealing process in an atmosphere containing a non-oxidizing gas and an oxidizing gas, and forming an upper electrode layer on the ferroelectric film.
摘要翻译：制造具有铁电电容器的半导体器件的方法包括以下步骤：在覆盖有源器件元件的绝缘膜上形成强电介质电容器的下电极层，在下电极层上形成作为电容器绝缘膜的铁电体膜，结晶所述铁电体膜通过在含有非氧化性气体和氧化性气体的气氛中进行热退火处理，在所述强电介质膜上形成上部电极层。

3. 发明授权

US06287637B1 Multi-layer approach for optimizing ferroelectric film performance 有权
标题翻译：用于优化铁电薄膜性能的多层方法
公开(公告)号：US06287637B1
公开(公告)日：2001-09-11
申请号：US09427644
申请日：1999-10-27
申请人： Fan Chu , Glen Fox , Brian Eastep
发明人： Fan Chu , Glen Fox , Brian Eastep
IPC分类号： C23C1408
CPC分类号： H01L28/56 , H01L29/516
摘要： A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.
摘要翻译：多层铁电薄膜包括成核层，本体层和任选的盖层。在底部电极上实施特定组成的薄的成核层以优化铁电晶体取向，并且与铁电体膜的主体中所需的组成显着不同。本体膜利用已建立的成核层作为其结晶生长的基础。实施多步沉积过程以实现期望的组成轮廓。该方法还允许在膜的上表面附近进行可选的第三组成调整，以确保与上电极界面的兼容性并补偿由后续处理产生的相互作用。

4. 发明授权

US06627930B1 Ferroelectric thin film capacitors having multi-layered crystallographic textures 失效
标题翻译：铁电薄膜电容器具有多层结构
公开(公告)号：US06627930B1
公开(公告)日：2003-09-30
申请号：US09525974
申请日：2000-03-14
申请人： Glen Fox , Fan Chu , Brian Eastep , Shan Sun
发明人： Glen Fox , Fan Chu , Brian Eastep , Shan Sun
IPC分类号： H01L27108
CPC分类号： H01L28/56
摘要： A ferroelectric thin film capacitor and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures. An integrated circuit device, such as a non-volatile memory device, includes at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.
摘要翻译：铁电薄膜电容器及其制造方法，其中电容器电介质包括多层晶体学结构。诸如非易失性存储器件的集成电路器件包括至少一个电容器，其具有顶部和底部电极以及它们之间的铁电介质层。所述铁电介质层包括形成所述电介质层的主体的第一结晶组织的第一铁电体层和在所述主体与所述顶部和底部电极中的一个之间形成界面层的具有第二不同结晶组织的第二铁电层。

5. 发明授权

US06376259B1 Method for manufacturing a ferroelectric memory cell including co-annealing 有权
标题翻译：包括共退火的铁电存储单元的制造方法
公开(公告)号：US06376259B1
公开(公告)日：2002-04-23
申请号：US09816425
申请日：2001-03-21
申请人： Fan Chu , Glen Fox
发明人： Fan Chu , Glen Fox
IPC分类号： H01L2100
CPC分类号： H01L28/55 , H01L21/76802
摘要： A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.
摘要翻译：铁电存储单元的制造方法包括在基板上形成底电极层，在底电极层上形成铁电薄膜层，在铁电薄膜层上形成上电极，在其上形成封装层的工序顶部电极，通过封装层形成接触孔，并在形成接触孔之后对铁电薄膜层和顶部电极进行共退火。

6. 发明授权

US06777287B2 Ferroelectric semiconductor memory device and a fabrication process thereof 有权
标题翻译：铁电半导体存储器件及其制造工艺
公开(公告)号：US06777287B2
公开(公告)日：2004-08-17
申请号：US10445124
申请日：2003-05-23
申请人： Soichiro Ozawa , Shan Sun , Hideyuki Noshiro , George Hickert , Katsuyoshi Matsuura , Fan Chu , Takeyasu Saito
发明人： Soichiro Ozawa , Shan Sun , Hideyuki Noshiro , George Hickert , Katsuyoshi Matsuura , Fan Chu , Takeyasu Saito
IPC分类号： H01L218242
CPC分类号： H01L27/11507 , H01L21/31691 , H01L27/11502 , H01L28/55
摘要： A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.
摘要翻译：铁电随机存取存储器具有由下电极，PZT膜和SrRuO 3的上电极堆叠而形成的铁电电容器，其中PZT膜包括针孔，针孔密度为约17μm2以下。

7. 发明申请

US20060245286A1 CIRCUIT FOR GENERATING A CENTERED REFERENCE VOLTAGE FOR A 1T/1C FERROELECTRIC MEMORY 有权
标题翻译：用于生成1T / 1C电磁存储器的中心参考电压的电路
公开(公告)号：US20060245286A1
公开(公告)日：2006-11-02
申请号：US11426165
申请日：2006-06-23
申请人： Shan SUN , Xiao-Hong Du , Fan Chu , Bob Sommervold
发明人： Shan SUN , Xiao-Hong Du , Fan Chu , Bob Sommervold
IPC分类号： G11C7/02
CPC分类号： G11C11/22 , G11C7/12 , G11C7/14
摘要： A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.
摘要翻译：铁电参考电路产生与（P + U）/ 2成比例的参考电压，并且在宽温度和电压范围内自动居中对应于P项和U项的位线电压。为了避免产生（P + U）/ 2的参考铁电电容器疲劳，参考电压每毫秒刷新一次。为了消除在这段时间内由于铁电电容器的泄漏引起的参考电压的变化，当刷新时，从参考铁电电容器产生的参考电压被数字化。数字值被固定并转换为模拟值，然后将其馈送到读出放大器中以解析数据状态。参考电压自动处于开关（P）和非开关（U）信号的中心，因此信号余量最大化。

8. 发明授权

US07116572B2 Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory 有权
标题翻译：用于产生1T / 1C铁电存储器的居中参考电压的电路
公开(公告)号：US07116572B2
公开(公告)日：2006-10-03
申请号：US10984065
申请日：2004-11-09
申请人： Shan Sun , Xiao-Hong Du , Fan Chu , Bob Sommervold
发明人： Shan Sun , Xiao-Hong Du , Fan Chu , Bob Sommervold
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/12 , G11C7/14
摘要： A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.
摘要翻译：铁电参考电路产生与（P + U）/ 2成比例的参考电压，并且在宽温度和电压范围内自动居中对应于P项和U项的位线电压。为了避免产生（P + U）/ 2的参考铁电电容器疲劳，参考电压每毫秒刷新一次。为了消除在这段时间内由于铁电电容器的泄漏引起的参考电压的变化，当刷新时，从参考铁电电容器产生的参考电压被数字化。数字值被固定并转换为模拟值，然后将其馈送到读出放大器中以解析数据状态。参考电压自动处于开关（P）和非开关（U）信号的中心，因此信号余量最大化。

9. 发明授权

US06617626B2 Ferroelectric semiconductor memory device and a fabrication process thereof 有权
公开(公告)号：US06617626B2
公开(公告)日：2003-09-09
申请号：US09797430
申请日：2001-02-28
申请人： Soichiro Ozawa , Shan Sun , Hideyuki Noshiro , George Hickert , Katsuyoshi Matsuura , Fan Chu , Takeyasu Saito
发明人： Soichiro Ozawa , Shan Sun , Hideyuki Noshiro , George Hickert , Katsuyoshi Matsuura , Fan Chu , Takeyasu Saito
IPC分类号： H01L2976
CPC分类号： H01L27/11507 , H01L21/31691 , H01L27/11502 , H01L28/55
摘要： A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17/&mgr;m2 or less.

10. 发明授权

US08081500B2 Method for mitigating imprint in a ferroelectric memory 有权
标题翻译：减轻铁电存储器印记的方法
公开(公告)号：US08081500B2
公开(公告)日：2011-12-20
申请号：US12415918
申请日：2009-03-31
申请人： Craig Taylor , Fan Chu , Shan Sun
发明人： Craig Taylor , Fan Chu , Shan Sun
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/1006 , G11C7/12 , G11C11/223 , G11C2207/002 , G11C2207/005
摘要： An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.
摘要翻译：允许压印缓解的铁电存储器单元的阵列包括分别耦合到字线，板线和位线的铁电存储器单元; 用于驱动字线的字线驱动器; 用于驱动板线的板线驱动器; 用于驱动位线的位线驱动器; 以及用于驱动耦合在位线和多个位线之间的隔离装置的隔离装置驱动器。减轻印记的方法包括将位线耦合到相应的多个读出放大器，打开字线并且脉冲与一排铁电存储器单元相关联的板线，将位线与相应的读出放大器断开，驱动板线低，位线高，驱动板线高位，位线低，驱动板线低电平，浮置位线，用读出放大器驱动位线，关闭字线并预充电位线。该方法可以在每次存储器访问之后执行，或者每当方便使用计数器和恢复命令时都可以执行该方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式