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1. 发明授权

US06627930B1 Ferroelectric thin film capacitors having multi-layered crystallographic textures 失效
标题翻译：铁电薄膜电容器具有多层结构
公开(公告)号：US06627930B1
公开(公告)日：2003-09-30
申请号：US09525974
申请日：2000-03-14
申请人： Glen Fox , Fan Chu , Brian Eastep , Shan Sun
发明人： Glen Fox , Fan Chu , Brian Eastep , Shan Sun
IPC分类号： H01L27108
CPC分类号： H01L28/56
摘要： A ferroelectric thin film capacitor and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures. An integrated circuit device, such as a non-volatile memory device, includes at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.
摘要翻译：铁电薄膜电容器及其制造方法，其中电容器电介质包括多层晶体学结构。诸如非易失性存储器件的集成电路器件包括至少一个电容器，其具有顶部和底部电极以及它们之间的铁电介质层。所述铁电介质层包括形成所述电介质层的主体的第一结晶组织的第一铁电体层和在所述主体与所述顶部和底部电极中的一个之间形成界面层的具有第二不同结晶组织的第二铁电层。

2. 发明授权

US06887716B2 Process for producing high quality PZT films for ferroelectric memory integrated circuits 有权
标题翻译：用于生产用于铁电存储器集成电路的高品质PZT膜的工艺
公开(公告)号：US06887716B2
公开(公告)日：2005-05-03
申请号：US09742204
申请日：2000-12-20
申请人： Glen Fox , Fan Chu , Brian Eastep , Tomohiro Takamatsu , Yoshimasa Horii , Ko Nakamura
发明人： Glen Fox , Fan Chu , Brian Eastep , Tomohiro Takamatsu , Yoshimasa Horii , Ko Nakamura
IPC分类号： H01L27/105 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8246 , H01L21/00
CPC分类号： H01L28/56 , H01L21/02197 , H01L21/02266 , H01L21/31691 , Y10S438/957
摘要： A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.
摘要翻译：制造集成电路的铁电电容器元件的方法包括沉积优选由贵金属制成的导电底电极层的步骤。底部电极被一层铁电介质材料覆盖。在沉积包含贵金属氧化物的第二电极层之前，用第一退火对铁电介质进行退火。导电性顶电极层的沉积之后，用第二次退火退火铁电电介质材料层和上电极层。第一和第二退火通过快速热退火进行。

3. 发明授权

US06287637B1 Multi-layer approach for optimizing ferroelectric film performance 有权
标题翻译：用于优化铁电薄膜性能的多层方法
公开(公告)号：US06287637B1
公开(公告)日：2001-09-11
申请号：US09427644
申请日：1999-10-27
申请人： Fan Chu , Glen Fox , Brian Eastep
发明人： Fan Chu , Glen Fox , Brian Eastep
IPC分类号： C23C1408
CPC分类号： H01L28/56 , H01L29/516
摘要： A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.
摘要翻译：多层铁电薄膜包括成核层，本体层和任选的盖层。在底部电极上实施特定组成的薄的成核层以优化铁电晶体取向，并且与铁电体膜的主体中所需的组成显着不同。本体膜利用已建立的成核层作为其结晶生长的基础。实施多步沉积过程以实现期望的组成轮廓。该方法还允许在膜的上表面附近进行可选的第三组成调整，以确保与上电极界面的兼容性并补偿由后续处理产生的相互作用。

4. 发明授权

US06376259B1 Method for manufacturing a ferroelectric memory cell including co-annealing 有权
标题翻译：包括共退火的铁电存储单元的制造方法
公开(公告)号：US06376259B1
公开(公告)日：2002-04-23
申请号：US09816425
申请日：2001-03-21
申请人： Fan Chu , Glen Fox
发明人： Fan Chu , Glen Fox
IPC分类号： H01L2100
CPC分类号： H01L28/55 , H01L21/76802
摘要： A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.
摘要翻译：铁电存储单元的制造方法包括在基板上形成底电极层，在底电极层上形成铁电薄膜层，在铁电薄膜层上形成上电极，在其上形成封装层的工序顶部电极，通过封装层形成接触孔，并在形成接触孔之后对铁电薄膜层和顶部电极进行共退火。

5. 发明申请

US20070090461A1 Ferroelectric Capacitor with Parallel Resistance for Ferroelectric Memory 有权
标题翻译：铁电存储器并联电阻的铁电电容器
公开(公告)号：US20070090461A1
公开(公告)日：2007-04-26
申请号：US11567873
申请日：2006-12-07
申请人： Jarrod Eliason , Glen Fox , Richard Bailey
发明人： Jarrod Eliason , Glen Fox , Richard Bailey
IPC分类号： H01L23/62
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/20 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).
摘要翻译：提出了铁电存储器单元（3），其中单元电容器（R）被集成到单元电容器（C）中，以在单元（3）不是单元电容器（3）时抑制电池存储节点（SN）处的电荷累积或电荷损耗在避免存储器单元访问操作的显着中断的同时被访问。提供方法（100,200）用于制造其中并联电阻（R）集成在电容器铁电材料（20）中或在形成的封装层（46）中的铁电存储器单元（3）和铁电电容器（C）超过图案化电容器结构（C）。

6. 发明申请

US20060118841A1 Ferroelectric capacitor with parallel resistance for ferroelectric memory 有权
标题翻译：用于铁电存储器的并联电阻的铁电电容器
公开(公告)号：US20060118841A1
公开(公告)日：2006-06-08
申请号：US11004708
申请日：2004-12-03
申请人： Jarrod Eliason , Glen Fox , Richard Bailey
发明人： Jarrod Eliason , Glen Fox , Richard Bailey
IPC分类号： H01L29/94
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/20 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).
摘要翻译：提出了铁电存储器单元（3），其中单元电容器（R）被集成到单元电容器（C）中，以在单元（3）不是单元电容器（3）时抑制电池存储节点（SN）处的电荷累积或电荷损耗在避免存储器单元访问操作的显着中断的同时被访问。提供方法（100,200）用于制造其中并联电阻（R）集成在电容器铁电材料（20）中或在形成的封装层（46）中的铁电存储器单元（3）和铁电电容器（C）超过图案化电容器结构（C）。

7. 发明授权

US06728093B2 Method for producing crystallographically textured electrodes for textured PZT capacitors 有权
公开(公告)号：US06728093B2
公开(公告)日：2004-04-27
申请号：US10190351
申请日：2002-07-03
申请人： Glen Fox
发明人： Glen Fox
IPC分类号： H01G4005
CPC分类号： H01L28/75 , H01L28/55
摘要： A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.

8. 发明申请

US20050199924A1 Optimized ferroelectric material crystallographic texture for enhanced high density feram 审中-公开
标题翻译：优化的铁电材料晶体学纹理，用于增强高密度的feram
公开(公告)号：US20050199924A1
公开(公告)日：2005-09-15
申请号：US10797503
申请日：2004-03-10
申请人： Glen Fox , Sanjeev Aggarwal , Richard Bailey
发明人： Glen Fox , Sanjeev Aggarwal , Richard Bailey
IPC分类号： H01L29/76
CPC分类号： H01L28/55 , H01L27/11507
摘要： Ferroelectric capacitors (CFE) are provided, having upper and lower conductive electrodes (22, 18) spaced along an axis (48), and a ferroelectric material (20) between the electrodes, where the ferroelectric material (20) comprises unit cells (200) individually comprising an elongated dimension (c), and where 50-90% of the unit cells in the ferroelectric material are oriented with elongated dimensions substantially parallel to the axis. Methods (100) are provided for fabricating ferroelectric capacitors in a wafer, comprising forming (112) a ferroelectric material above a lower electrode material, the ferroelectric material comprising unit cells with an elongated dimension, wherein 50-90% of the unit cells are oriented with elongated dimensions substantially normal to an upper surface of the wafer.
摘要翻译：提供铁电电容器（C FE），其具有沿轴线（48）间隔开的上导电电极（22）和下导电电极（22,18）和电极之间的铁电材料（20），其中铁电材料（20）包括分别包括细长尺寸（c）的单元电池（200），并且其中铁电材料中的50-90％的单元电池被取向为基本上平行于该轴线的细长尺寸。提供了用于在晶片中制造铁电电容器的方法（100），包括在下电极材料上形成（112）铁电材料，所述铁电材料包括具有细长尺寸的单元电池，其中50-90％的单元电池定向具有基本上垂直于晶片的上表面的细长尺寸。

9. 发明授权

US06853535B2 Method for producing crystallographically textured electrodes for textured PZT capacitors 失效
标题翻译：用于纹理PZT电容器的晶体学纹理电极的制造方法
公开(公告)号：US06853535B2
公开(公告)日：2005-02-08
申请号：US10190350
申请日：2002-07-03
申请人： Glen Fox , Thomas Davenport
发明人： Glen Fox , Thomas Davenport
IPC分类号： H01L21/02 , H01G4/005
CPC分类号： H01L28/75 , H01L28/55
摘要： A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic (“FCC”) structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM® memory and other microelectronic devices.
摘要翻译：描述了底部电极结构和制造方法，用于制造晶体学织构的铱电极，用于制造具有增强的铁电存储器性能的织构化PZT电容器。使用源自具有{0001}纹理的六方晶系结构的种子层提供了表现出面心立方（“FCC”）结构的{111}织构铱生长的光滑表面。这种播种技术导致{111}纹理铱，相对于膜厚度具有小的表面粗糙度。高度纹理的铱支持{111}织构化的PZT介电层生长。纹理PZT表现出增强的开关极化，降低工作电压，并且还提高了FRAM（R）存储器和其他微电子器件中使用的PZT电容器的可靠性。

10. 发明授权

US06597028B2 Capacitively coupled ferroelectric random access memory cell and a method for manufacturing the same 有权
公开(公告)号：US06597028B2
公开(公告)日：2003-07-22
申请号：US09873772
申请日：2001-06-04
申请人： Glen Fox , Thomas Evans
发明人： Glen Fox , Thomas Evans
IPC分类号： H01C2974
CPC分类号： H01L28/55 , H01L21/76895 , H01L27/11507 , H01L28/60
摘要： A ferroelectric memory cell includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.

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