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1. 发明授权

US08916434B2 Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process 有权
标题翻译：用于控制F-RAM工艺中铁电电容器氢诱导退化的增强氢气阻挡封装方法
公开(公告)号：US08916434B2
公开(公告)日：2014-12-23
申请号：US13470117
申请日：2012-05-11
申请人： Shan Sun , Thomas E. Davenport
发明人： Shan Sun , Thomas E. Davenport
IPC分类号： H01L29/76
CPC分类号： H01L28/40 , H01L23/291 , H01L27/11502 , H01L27/11507 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： A method of encapsulating a ferroelectric capacitor or ferroelectric memory cell includes forming encapsulation materials adjacent to a ferroelectric capacitor. forming a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and forming an FEO encapsulation layer over the ferroelectric oxide to provide additional protection from hydrogen induced degradation.
摘要翻译：封装铁电电容器或铁电存储单元的方法包括形成与铁电电容器相邻的封装材料。在封装的铁电电容器上形成铁电氧化物（FEO）层，并在铁电氧化物上形成一个FEO封装层，以提供额外的防止氢诱导退化的保护。

2. 发明授权

US08518792B2 Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure 有权
标题翻译：用于制造具有与三维晶体管结构对准的铁电电容器的镶嵌自对准铁电随机存取存储器（F-RAM）的方法
公开(公告)号：US08518792B2
公开(公告)日：2013-08-27
申请号：US13569785
申请日：2012-08-08
申请人： Shan Sun , Thomas E. Davenport , John Cronin
发明人： Shan Sun , Thomas E. Davenport , John Cronin
IPC分类号： H01L21/20
CPC分类号： H01L43/02 , H01L27/11504 , H01L27/11507 , H01L27/228
摘要： Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
摘要翻译：公开了一种非易失性铁电随机存取存储器（F-RAM）装置和一种用于制造镶嵌自对准F-RAM的方法，其允许形成具有与预先存在的三维对准的分离的PZT层的铁电电容器（3-D）晶体管结构。

3. 发明申请

US20120293474A1 SYSTEMS AND METHODS FOR FACILITATING LIFT-OFF PROCESSES 审中-公开
标题翻译：促进提升过程的系统和方法
公开(公告)号：US20120293474A1
公开(公告)日：2012-11-22
申请号：US13233667
申请日：2011-09-15
申请人： I-Shan Sun , Francois Hebert , Rick Carlton Jerome
发明人： I-Shan Sun , Francois Hebert , Rick Carlton Jerome
IPC分类号： G09G5/10 , B05D1/36 , B05D5/06 , G01J1/42 , G01J1/02
CPC分类号： G01J1/0488 , G01J1/42 , G01J1/4204 , G09G2360/144
摘要： Systems and methods for facilitating lift-off processes are provided. In one embodiment, a method for pattering a thin film on a substrate comprises: depositing a first sacrificial layer of photoresist material onto a substrate such that one or more regions of the substrate are exposed through the first sacrificial layer; depositing a protective layer over at least part of the first sacrificial layer; partially removing the first sacrificial layer to form at least one gap between the protective layer and the substrate; depositing an optical coating over the protective layer and the one or more regions of the substrate exposed through the first sacrificial layer, wherein the optical coating deposited over the protective layer is separated by the at least one gap from the optical coating deposited over the regions of the substrate exposed through the first sacrificial layer; and removing the first sacrificial layer.
摘要翻译：提供了用于促进剥离过程的系统和方法。在一个实施例中，用于在衬底上图案化薄膜的方法包括：将光致抗蚀剂材料的第一牺牲层沉积到衬底上，使得衬底的一个或多个区域通过第一牺牲层暴露; 在第一牺牲层的至少一部分上沉积保护层; 部分地去除所述第一牺牲层以在所述保护层和所述衬底之间形成至少一个间隙; 在所述保护层上沉积光学涂层，并且通过所述第一牺牲层暴露出所述衬底的所述一个或多个区域，其中沉积在所述保护层上的所述光学涂层被所述光学涂层的所述至少一个间隙与沉积在所述衬底通过所述第一牺牲层暴露; 以及去除所述第一牺牲层。

4. 发明授权

US08081500B2 Method for mitigating imprint in a ferroelectric memory 有权
标题翻译：减轻铁电存储器印记的方法
公开(公告)号：US08081500B2
公开(公告)日：2011-12-20
申请号：US12415918
申请日：2009-03-31
申请人： Craig Taylor , Fan Chu , Shan Sun
发明人： Craig Taylor , Fan Chu , Shan Sun
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/1006 , G11C7/12 , G11C11/223 , G11C2207/002 , G11C2207/005
摘要： An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.
摘要翻译：允许压印缓解的铁电存储器单元的阵列包括分别耦合到字线，板线和位线的铁电存储器单元; 用于驱动字线的字线驱动器; 用于驱动板线的板线驱动器; 用于驱动位线的位线驱动器; 以及用于驱动耦合在位线和多个位线之间的隔离装置的隔离装置驱动器。减轻印记的方法包括将位线耦合到相应的多个读出放大器，打开字线并且脉冲与一排铁电存储器单元相关联的板线，将位线与相应的读出放大器断开，驱动板线低，位线高，驱动板线高位，位线低，驱动板线低电平，浮置位线，用读出放大器驱动位线，关闭字线并预充电位线。该方法可以在每次存储器访问之后执行，或者每当方便使用计数器和恢复命令时都可以执行该方法。

5. 发明授权

US08073182B2 Mounting apparatus for speaker 有权
标题翻译：扬声器安装装置
公开(公告)号：US08073182B2
公开(公告)日：2011-12-06
申请号：US12347340
申请日：2008-12-31
申请人： Wen-Bo Li , Yang Xiao , Hai-Shan Sun
发明人： Wen-Bo Li , Yang Xiao , Hai-Shan Sun
IPC分类号： H04R1/02
CPC分类号： H04R1/025
摘要： A mounting apparatus for mounting a speaker to a computer case, includes a base plate assembled on the computer case, a fixing member configured to fix two corners on a top edge of the speaker, and an elastic sheet configured to fix a bottom edge of the speaker.
摘要翻译：一种用于将扬声器安装到计算机外壳的安装装置，包括组装在计算机外壳上的底板，固定构件，用于将扬声器的顶部边缘上的两个角部固定;以及弹性片，扬声器。

6. 发明申请

US20100246238A1 METHOD FOR MITIGATING IMPRINT IN A FERROELECTRIC MEMORY 有权
标题翻译：减少电磁记忆中印痕的方法
公开(公告)号：US20100246238A1
公开(公告)日：2010-09-30
申请号：US12415918
申请日：2009-03-31
申请人： Craig Taylor , Fan Chu , Shan Sun
发明人： Craig Taylor , Fan Chu , Shan Sun
IPC分类号： G11C11/22 , G11C7/00 , G11C8/08
CPC分类号： G11C11/22 , G11C7/1006 , G11C7/12 , G11C11/223 , G11C2207/002 , G11C2207/005
摘要： An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.
摘要翻译：允许压印缓解的铁电存储器单元的阵列包括分别耦合到字线，板线和位线的铁电存储器单元; 用于驱动字线的字线驱动器; 用于驱动板线的板线驱动器; 用于驱动位线的位线驱动器; 以及用于驱动耦合在位线和多个位线之间的隔离装置的隔离装置驱动器。减轻印记的方法包括将位线耦合到相应的多个读出放大器，打开字线并且脉冲与一排铁电存储器单元相关联的板线，将位线与相应的读出放大器断开，驱动板线低，位线高，驱动板线高位，位线低，驱动板线低电平，浮置位线，用读出放大器驱动位线，关闭字线并预充电位线。该方法可以在每次存储器访问之后执行，或者每当方便使用计数器和恢复命令时都可以执行该方法。

7. 发明申请

US20100165591A1 ELECTRONIC DEVICE ENCLOSURE 失效
标题翻译：电子设备外壳
公开(公告)号：US20100165591A1
公开(公告)日：2010-07-01
申请号：US12482906
申请日：2009-06-11
申请人： CHIN-WEN YEH , ZHI-JIAN PENG , HAI-SHAN SUN
发明人： CHIN-WEN YEH , ZHI-JIAN PENG , HAI-SHAN SUN
IPC分类号： H05K5/00
CPC分类号： H05K7/1429 , H05K7/1402
摘要： An enclosure for an electronic device includes a chassis and a cover. The chassis includes a bottom wall and an opening. A circuit board is mounted on the bottom wall. The cover is mounted on the chassis to cover the opening of the chassis. A fixing apparatus is movably mounted on the cover. The fixing apparatus contacts and biases the expansion card toward the circuit board.
摘要翻译：电子设备的外壳包括底盘和盖子。底盘包括底壁和开口。电路板安装在底壁上。盖子安装在机箱上以覆盖机箱的开口。定影装置可移动地安装在盖上。定影装置将扩展卡朝向电路板接触并偏压。

8. 发明授权

US07313010B2 Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory 有权
标题翻译：用于产生1T / 1C铁电存储器的居中参考电压的电路
公开(公告)号：US07313010B2
公开(公告)日：2007-12-25
申请号：US11426165
申请日：2006-06-23
申请人： Shan Sun , Xiao-Hong Du , Fan Chu , Bob Sommervold
发明人： Shan Sun , Xiao-Hong Du , Fan Chu , Bob Sommervold
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/12 , G11C7/14
摘要： A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.
摘要翻译：铁电参考电路产生与（P + U）/ 2成比例的参考电压，并且在宽温度和电压范围内自动居中对应于P项和U项的位线电压。为了避免产生（P + U）/ 2的参考铁电电容器疲劳，参考电压每毫秒刷新一次。为了消除在这段时间内由于铁电电容器的泄漏引起的参考电压的变化，当刷新时，从参考铁电电容器产生的参考电压被数字化。数字值被固定并转换为模拟值，然后将其馈送到读出放大器中以解析数据状态。参考电压自动处于开关（P）和非开关（U）信号的中心，因此信号余量最大化。

9. 发明申请

US20060098470A1 Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory 有权
公开(公告)号：US20060098470A1
公开(公告)日：2006-05-11
申请号：US10984065
申请日：2004-11-09
申请人： Shan Sun , Xiao-Hong Du , Fan Chu , Bob Sommervold
发明人： Shan Sun , Xiao-Hong Du , Fan Chu , Bob Sommervold
IPC分类号： G11C11/22 , G11C5/14
CPC分类号： G11C11/22 , G11C7/12 , G11C7/14
摘要： A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

10. 发明申请

US20060060941A1 Polysilicon sidewall spacer lateral bipolar transistor on SOI 审中-公开
标题翻译： SOI上的多晶硅侧壁间隔物横向双极晶体管
公开(公告)号：US20060060941A1
公开(公告)日：2006-03-23
申请号：US11210881
申请日：2005-08-25
申请人： I-Shan Sun , Wai Ng , Koji Kanekiyo
发明人： I-Shan Sun , Wai Ng , Koji Kanekiyo
IPC分类号： H01L29/00
CPC分类号： H01L29/0821 , H01L29/1008 , H01L29/42304 , H01L29/66265 , H01L29/7317
摘要： Consistent with an aspect of the present invention, a lateral bipolar transistor is provided that exhibits similar performance as that of high speed vertical bipolar junction transistors. The lateral bipolar transistor includes a polysilicon side-wall-spacer (PSWS) that forms a contact with the base of the transistor, and thus avoids the process step of aligning a contact mask to a relatively thin base region. The side wall spacer allows self-alignment of the base/emitter region, and has reduced base resistance and junction capacitance. Accordingly, improved cutoff frequency (fτ) and maximum oscillation frequency (fmax) can be achieved. Moreover, this novel topology enables the realization of Bipolar CMOS (BiCMOS) technology on insulating substrates, such as SOI.
摘要翻译：根据本发明的一个方面，提供了一种横向双极晶体管，其表现出与高速垂直双极结型晶体管相似的性能。横向双极晶体管包括与晶体管的基极形成接触的多晶硅侧壁间隔物（PSWS），从而避免了将接触掩模对准相对薄的基极区域的工艺步骤。侧壁间隔物允许基极/发射极区域的自对准，并且具有降低的基极电阻和结电容。因此，可以实现改进的截止频率（ftau）和最大振荡频率（fmax）。此外，这种新颖的拓扑结构使得能够在诸如SOI的绝缘衬底上实现双极CMOS（BiCMOS）技术。

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