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    • 5. 发明授权
    • Low-noise amplifier stage with matching network
    • 具有匹配网络的低噪声放大器级
    • US06278329B1
    • 2001-08-21
    • US09466573
    • 1999-12-21
    • Giuseppe PalmisanoGiuseppe FerlaGiovanni Girlando
    • Giuseppe PalmisanoGiuseppe FerlaGiovanni Girlando
    • H03F304
    • H03F1/22H03F1/565H03F2200/294H03F2200/372
    • An amplifier stage having a first and a second transistor connected in series to each other between a first and a second reference potential line. The first transistor has a control terminal connected to an input of the amplifier stage through a first inductor, a first terminal connected to the second reference potential line through a second inductor, and a third terminal connected to a first terminal of the second transistor. The second transistor has a second terminal forming an output of the amplifier stage, and connected to the first reference potential line through a load resistor. To improve the noise figure, a matching capacitor is connected between the control terminal and the first terminal of the first transistor.
    • 具有在第一和第二参考电位线之间彼此串联连接的第一和第二晶体管的放大器级。 第一晶体管具有通过第一电感器连接到放大器级的输入的控制端子,通过第二电感器连接到第二参考电位线的第一端子和连接到第二晶体管的第一端子的第三端子。 第二晶体管具有形成放大器级的输出的第二端子,并通过负载电阻器连接到第一参考电位线。 为了提高噪声系数,在控制端子与第一晶体管的第一端子之间连接有匹配电容器。
    • 8. 发明申请
    • METHOD FOR MANUFACTURING A HIGH INTEGRATION DENSITY POWER MOS DEVICE
    • 用于制造高集成度密度功率MOS器件的方法
    • US20090321826A1
    • 2009-12-31
    • US12551999
    • 2009-09-01
    • Giuseppe ARENAGiuseppe FerlaMarco Camalleri
    • Giuseppe ARENAGiuseppe FerlaMarco Camalleri
    • H01L29/78
    • H01L29/7802H01L21/2815H01L29/42372H01L29/42376H01L29/4238H01L29/4933H01L29/66712
    • A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.
    • 用于实现高集成度功率MOS器件的方法包括以下步骤:提供具有第一类型导电性的掺杂半导体衬底; 在所述基板上形成具有较低导电率的半导体层; 在半导体层上形成厚度介于3000和13000A(埃)之间的介电层; 在电介质层上沉积硬掩模层; 通过掩模层掩蔽硬掩模层; 蚀刻硬掩模层和下面的介电层以限定多个硬掩模部分以保护所述介电层; 去除掩蔽层; 各向同性和横向蚀刻所述介电层,在所述硬掩模部分下面的所述介电层中形成横向空腔; 形成厚度为150至1500A(埃)的栅极氧化物,其在所述空腔中沉积导体材料并且在其上方,以形成与包括所述厚介电层和所述栅极氧化物的栅极结构完全对准的凹陷间隔物。