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1. 发明授权

US09229031B2 Probes for testing integrated electronic circuits and corresponding production method 有权
标题翻译：集成电子电路检测探针及相应的生产方法
公开(公告)号：US09229031B2
公开(公告)日：2016-01-05
申请号：US13106615
申请日：2011-05-12
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/20 , G01R1/067 , G01R3/00 , G01R31/319 , G01R1/073
CPC分类号： G01R3/00 , G01R1/06761 , G01R1/07307 , G01R1/07342 , G01R31/31905 , Y10T29/49002
摘要： An embodiment of a method is proposed for producing cantilever probes for use in a test apparatus of integrated electronic circuits; the probes are configured to contact during the test corresponding terminals of the electronic circuits to be tested. An embodiment comprises forming probe bodies of electrically conductive materials. In an embodiment, the method further includes forming on a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.
摘要翻译：提出了一种用于制造用于集成电子电路的测试装置的悬臂探针的方法的实施例; 探针被配置为在测试的电子电路的相应端子的测试期间接触。一个实施例包括形成导电材料的探针体。在一个实施例中，该方法还包括在每个探针体的下部形成在使用中的，被引导到要接触的相应端子的第一硬度值等于或大于300HV的导电接触区域; 每个接触区域和相应的探针体形成相应的探针。

2. 发明授权

US08928346B2 Method for an improved checking of repeatability and reproducibility of a measuring chain for semiconductor device testing 有权
标题翻译：用于半导体器件测试的测量链的重复性和再现性的改进的检查方法
公开(公告)号：US08928346B2
公开(公告)日：2015-01-06
申请号：US13092772
申请日：2011-04-22
申请人： Sergio Tenucci , Alberto Pagani , Marco Spinetta , Bernard Ranchoux
发明人： Sergio Tenucci , Alberto Pagani , Marco Spinetta , Bernard Ranchoux
IPC分类号： G01R31/26 , G05B19/418 , G01R31/28
CPC分类号： G05B19/41875 , G01R31/2894 , Y02P90/22 , Y02P90/86
摘要： A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.
摘要翻译：一种方法提供了对测量链的重复性和再现性的改进的检查，特别是通过半导体器件测试的质量控制。该方法包括对通过测量系统进行测量或控制的多个和不同设备提供的测试步骤，所述测量系统包括测试装置（ATE）和要进行测量或控制的每个设备之间的至少一个测量单元链。有利地，该方法包括检查构成测量链的一部分的每种类型的单元的重复性和再现性，并且在检查之后，使各种测量链之间的相关性作为整体来检查重复性和再现性，使用受到测量或控制。

3. 发明授权

US08907693B2 Electromagnetic shield for testing integrated circuits 有权
标题翻译：用于测试集成电路的电磁屏蔽
公开(公告)号：US08907693B2
公开(公告)日：2014-12-09
申请号：US12851680
申请日：2010-08-06
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/28 , G01R1/18 , G01R1/067 , G01R1/073
CPC分类号： G01R1/18 , G01R1/06772 , G01R1/07307 , G01R31/2884 , G01R31/2886
摘要： An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.
摘要翻译：提出了一种探针卡的实施例。探针卡包括多个探针。每个探针适于在晶片的测试阶段期间接触集成在半导体材料晶片的至少一个管芯中的电路的相应端子。所述多个探头包括适于在测试阶段期间向/从相应终端提供和/或接收射频测试信号的至少一个探头。所述探针卡包括对应于所述至少一个探头的至少一个电磁屏蔽结构，所述至少一个探针适于提供和/或接收射频测试信号，用于对由至少一个探头照射的电磁场的至少部分屏蔽， /或接收射频测试信号。

4. 发明申请

US20130027073A1 INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA 有权
标题翻译：整合电路至少包含一个集成天线
公开(公告)号：US20130027073A1
公开(公告)日：2013-01-31
申请号：US13560632
申请日：2012-07-27
申请人： Alberto Pagani , Alessandro Finocchiaro
发明人： Alberto Pagani , Alessandro Finocchiaro
IPC分类号： G01R1/00 , H01L29/02
CPC分类号： H01L28/10 , G01R31/2834 , G01R31/2889 , G01R31/3025 , H01L22/32 , H01L22/34 , H01L23/528 , H01L23/544 , H01L23/564 , H01L23/585 , H01L23/66 , H01L24/05 , H01L25/0657 , H01L29/0642 , H01L2223/6677 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/16225 , H01L2224/48091 , H01L2224/48465 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.
摘要翻译：一种在基板上的集成电路，其包括至少一个围绕有源区域的外围部分，并且靠近至少一个切割线实现，该切割线提供与在同一晶片上实现的其它集成电路的分离。该集成电路包括至少一个导电结构，其在从基板开始的不同平面的周边部分中延伸，并实现用于该电路的集成天线。

5. 发明申请

US20110186838A1 CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER 有权
标题翻译：用于在半导体波形集成的大量电子器件进行电气或电磁测试期间并联供电的电路架构
公开(公告)号：US20110186838A1
公开(公告)日：2011-08-04
申请号：US13022419
申请日：2011-02-07
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： H01L23/48 , H01L21/66
CPC分类号： H01L22/32 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.
摘要翻译：电路架构提供了在同一半导体晶片上并且由划线界定的电子设备的电或电磁测试期间并联供电。电路架构包括将电子设备互连并且具有设备外部的部分和设备内部的部分的导电栅格。外部部分沿划线延伸; 并且内部部分在装置的至少一部分内延伸。电路结构包括在导电栅格的外部部分和内部部分之间并且设置在至少一部分器件上的互连焊盘，互连焊盘与内部和外部部分形成不同的电源线电子设备组。

6. 发明申请

US20110089962A1 TESTING OF ELECTRONIC DEVICES THROUGH CAPACITIVE INTERFACE 有权
标题翻译：通过电容接口测试电子设备
公开(公告)号：US20110089962A1
公开(公告)日：2011-04-21
申请号：US12907839
申请日：2010-10-19
申请人： Alberto PAGANI
发明人： Alberto PAGANI
IPC分类号： G01R31/312 , G01R1/06 , G01R31/302
CPC分类号： G01R1/06761 , G01R1/06711 , G01R1/06716 , G01R1/06733 , G01R1/06766 , G01R1/07 , G01R1/07314 , G01R31/312
摘要： An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.
摘要翻译：一种用于执行具有多个导电端子的电子装置的测试的测试装置的实施例，所述测试装置包括用于与端子交换电信号的多个导电测试探针，以及用于机械耦合用电子设备测试探头。在一个实施例中，耦合装置包括绝缘装置，用于在执行测试期间将至少部分测试探针中的每一个与至少一个相应的端子电绝缘。每个测试探头和相应的端子形成用于将测试探头与端子电磁耦合的电容器。

7. 发明申请

US20110050267A1 ELECTROMAGNETIC SHIELD FOR TESTING INTEGRATED CIRCUITS 有权
标题翻译：用于测试集成电路的电磁屏蔽
公开(公告)号：US20110050267A1
公开(公告)日：2011-03-03
申请号：US12851680
申请日：2010-08-06
申请人： Alberto PAGANI
发明人： Alberto PAGANI
IPC分类号： G01R31/00 , G01R1/06
CPC分类号： G01R1/18 , G01R1/06772 , G01R1/07307 , G01R31/2884 , G01R31/2886
摘要： An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.
摘要翻译：提出了一种探针卡的实施例。探针卡包括多个探针。每个探针适于在晶片的测试阶段期间接触集成在半导体材料晶片的至少一个管芯中的电路的相应端子。所述多个探头包括适于在测试阶段期间向/从相应终端提供和/或接收射频测试信号的至少一个探头。所述探针卡包括对应于所述至少一个探头的至少一个电磁屏蔽结构，所述至少一个探针适于提供和/或接收射频测试信号，用于对由至少一个探头照射的电磁场的至少部分屏蔽， /或接收射频测试信号。

8. 发明申请

US20100134133A1 METHOD FOR PERFORMING AN ELECTRICAL TESTING OF ELECTRONIC DEVICES 有权
标题翻译：用于执行电子设备电气测试的方法
公开(公告)号：US20100134133A1
公开(公告)日：2010-06-03
申请号：US12625188
申请日：2009-11-24
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/02
CPC分类号： G01R31/31713
摘要： A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel.
摘要翻译：一种电气测试电子设备DUT的方法，包括：至少将电子设备DUT连接到适于执行数字电路或存储器或数字电路和存储器的测试的自动测试设备; 通过ATE设备向电子设备DUT发送电测试命令信号; 通过至少一个高级监督自检系统“内置在电子设备DUT”中的“高级低引脚数BIST”ALB进行电子设备DUT的电气测试，ALB系统通过专用数字通信与ATE进行数字接口渠道; 并且通过数字通信信道向电子设备DUT向ATE设备发送包括测量，故障信息和答复数据的回复消息（如果有的话）到命令信号。

9. 发明授权

US09097637B2 Integrated electronic device for monitoring parameters within a solid structure and monitoring system using such a device 有权
标题翻译：集成电子设备，用于监测实体结构中的参数和使用这种设备的监控系统
公开(公告)号：US09097637B2
公开(公告)日：2015-08-04
申请号：US13996259
申请日：2011-10-20
申请人： Alberto Pagani , Bruno Murari
发明人： Alberto Pagani , Bruno Murari
IPC分类号： G01N27/00 , G01M5/00 , G01L1/26
CPC分类号： G01N27/00 , G01L1/26 , G01M5/0083
摘要： An electronic device is for detecting and monitoring a local parameter within a solid structure. The electronic device may include an integrated detection module having a functional IC including an integrated sensor to detect the local parameter within the solid structure, and an antenna and having a functional circuitry surface facing towards an outside of the functional IC, and a passivation layer to cover at least the functional circuitry surface of the functional IC so that the functional IC is hermetically sealed and galvanically insulated from a surrounding environment. The electronic device may also include an RF circuit to be coupled with the integrated detection module and having a remote antenna configured to transmit/receive signals for telecommunications and energy exchange with the antenna. The antenna, the RF circuit, and the remote antenna may wirelessly communicate via an electromagnetic coupling.
摘要翻译：电子设备用于检测和监视固体结构内的局部参数。电子设备可以包括具有功能IC的集成检测模块，该功能IC包括用于检测固体结构内的局部参数的集成传感器，以及具有面向功能IC外部的功能电路表面的天线，以及钝化层至少覆盖功能IC的功能电路表面，使得功能IC与周围环境气密密封和电隔离。电子设备还可以包括要与集成检测模块耦合的RF电路，并且具有被配置为发送/接收用于与天线的电信和能量交换的信号的远程天线。天线，RF电路和远程天线可以通过电磁耦合进行无线通信。

10. 发明授权

US09008785B2 Retinal prosthesis 有权
标题翻译：视网膜假体
公开(公告)号：US09008785B2
公开(公告)日：2015-04-14
申请号：US13977121
申请日：2011-12-30
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： A61F2/14 , A61F9/08 , A61N1/05 , A61N1/36
CPC分类号： A61F2/14 , A61F2/148 , A61F9/08 , A61F2250/0002 , A61N1/0543 , A61N1/36 , A61N1/36046
摘要： A retinal prosthesis including an electronic stimulation unit housed inside an eye and including: a plurality of electrodes that contact a portion of a retina of the eye; an electronic control circuit, which is electrically connected to the electrodes and supplies to the electrodes electrical stimulation signals designed to stimulate the portion of retina; and a local antenna connected to the electronic control circuit. The retinal prosthesis further includes an electromagnetic expansion housed inside the eye and formed by a first expansion antenna and a second expansion antenna electrically connected together, the first expansion antenna being magnetically or electromagnetically coupled to an external antenna, the second expansion antenna being magnetically or electromagnetically couple to the local antenna, the electromagnetic expansion moreover receiving an electromagnetic supply signal transmitted by the external antenna and generating a corresponding replica signal.
摘要翻译：一种视网膜假体，包括容纳在眼睛内的电子刺激单元，包括：多个电极，其接触眼睛的视网膜的一部分; 电子控制电路，电连接到电极并向电极提供设计成刺激视网膜部分的电刺激信号; 以及连接到电子控制电路的本地天线。视网膜假体还包括容纳在眼睛内部并由第一扩展天线和电连接在一起的第二扩展天线形成的电磁膨胀，第一扩展天线被磁或电磁耦合到外部天线，第二扩展天线是磁性或电磁学的耦合到本地天线，电磁膨胀还接收由外部天线发送的电磁供给信号并产生相应的复制信号。

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