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1. 发明授权

US09018635B2 Integrated electronic device with edge-termination structure and manufacturing method thereof 有权
标题翻译：具有边缘终端结构的集成电子装置及其制造方法
公开(公告)号：US09018635B2
公开(公告)日：2015-04-28
申请号：US13221778
申请日：2011-08-30
申请人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
IPC分类号： H01L29/16 , H01L29/78 , H01L29/267 , H01L29/06 , H01L29/10 , H01L29/40
CPC分类号： H01L29/66666 , H01L21/02529 , H01L21/02532 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/66431 , H01L29/7811 , H01L29/7813
摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
摘要翻译：一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

2. 发明授权

US08664713B2 Integrated power device on a semiconductor substrate having an improved trench gate structure 有权
标题翻译：具有改进的沟槽栅结构的半导体衬底上的集成功率器件
公开(公告)号：US08664713B2
公开(公告)日：2014-03-04
申请号：US12645255
申请日：2009-12-22
申请人： Angelo Magri , Antonino Sebastiano Alessandria , Stefania Fortuna , Leonardo Fragapane
发明人： Angelo Magri , Antonino Sebastiano Alessandria , Stefania Fortuna , Leonardo Fragapane
IPC分类号： H01L29/66
CPC分类号： H01L29/1037 , H01L29/405 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4916 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
摘要翻译：集成在半导体衬底上并在沟槽栅极结构内具有多个导电桥的功率器件。在一个实施例中，半导体衬底包括具有侧壁和底部的沟槽，壁和底部被第一绝缘涂层覆盖，然后第一绝缘涂层还包括导电栅极结构。一个实施例提供形成导电栅极结构，至少用第一导电材料的第二导电涂层覆盖侧壁。这导致第二导电材料的导电中心区域具有与第一导电材料不同的电阻率，该第一导电材料在所述第二导电涂层和所述导电中心区域之间形成多个导电桥。

3. 发明申请

US20120056200A1 INTEGRATED ELECTRONIC DEVICE WITH EDGE-TERMINATION STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有边缘结构的集成电子设备及其制造方法
公开(公告)号：US20120056200A1
公开(公告)日：2012-03-08
申请号：US13221778
申请日：2011-08-30
申请人： Ferruccio FRISINA , Angelo MAGRI' , Mario Giuseppe SAGGIO
发明人： Ferruccio FRISINA , Angelo MAGRI' , Mario Giuseppe SAGGIO
IPC分类号： H01L29/16 , H01L21/20 , H01L21/02 , H01L29/06
CPC分类号： H01L29/66666 , H01L21/02529 , H01L21/02532 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/66431 , H01L29/7811 , H01L29/7813
摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
摘要翻译：一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

4. 发明申请

US20110049638A1 STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS 审中-公开
标题翻译：高压器件结构与相应的集成工艺
公开(公告)号：US20110049638A1
公开(公告)日：2011-03-03
申请号：US12868023
申请日：2010-08-25
申请人： Mario Giuseppe SAGGIO , Domenico MURABITO , Angelo MAGRI'
发明人： Mario Giuseppe SAGGIO , Domenico MURABITO , Angelo MAGRI'
IPC分类号： H01L27/088 , H01L29/06 , H01L21/8234
CPC分类号： H01L29/0634 , H01L27/088 , H01L29/0649 , H01L29/086 , H01L29/1095 , H01L29/41766 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7811
摘要： An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
摘要翻译：一种用于高压器件的结构的实施例，其包括至少半导体衬底被第一导电类型的外延层覆盖，其中实现了多个柱结构，哪些柱结构包括高纵横比深度所述外延层又被活性表面积覆盖，其中所述高电压器件被实现，所述列结构中的至少一个外部部分又由第二导电类型的硅外延层实现，所述硅外延层相反比所述第一类型的导电性和具有使在所述列结构之外的所述外延层中的掺杂剂电荷平衡的掺杂剂电荷以及在所述外部部分内部实现的电介质填充部分，以便完全填充所述深沟槽。

5. 发明授权

US07800173B2 Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture 有权
标题翻译：因此制造具有不同厚度的栅极电介质结构和垂直导通MISFET器件的垂直导通MISFET器件的制造工艺
公开(公告)号：US07800173B2
公开(公告)日：2010-09-21
申请号：US12074226
申请日：2008-02-29
申请人： Orazio Battiato , Domenico Repici , Fabrizio Marco Di Paola , Giuseppe Arena , Angelo Magri′
发明人： Orazio Battiato , Domenico Repici , Fabrizio Marco Di Paola , Giuseppe Arena , Angelo Magri′
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0856 , H01L29/0878 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/66719
摘要： According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.
摘要翻译：根据用于制造MISFET器件的方法的实施例，在半导体晶片中，形成具有第一类型的导电性和第一级掺杂的半导体层。在半导体层中形成有具有与第一类型的导电性相反的第二导电类型的第一体区和第二体区，以及在第一和第二体区之间延伸的富集区。富集区具有第一类导电性和第二级掺杂，高于第一级掺杂。此外，在富集区域和第一和第二体区的一部分之上形成栅电极，并且在栅极电极和半导体层之间形成介电栅极结构，在富集区域上具有较大厚度的电介质栅极结构并且在第一和第二身体区域上具有较小的厚度。为了形成富集区域，在半导体层上形成第一导电层，在第一导电层中形成富集开口，并且通过富集开口将掺杂剂物质引入半导体层。此外，介电栅极结构的形成设想在形成第一体区域和第二体区域之前用电介质材料填充富集开口。

6. 发明申请

US20080211021A1 Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture 有权
标题翻译：因此制造具有不同厚度的栅极电介质结构和垂直导通MISFET器件的垂直导通MISFET器件的制造工艺
公开(公告)号：US20080211021A1
公开(公告)日：2008-09-04
申请号：US12074226
申请日：2008-02-29
申请人： Orazio Battiato , Domenico Repici , Fabrizio Marco Di Paola , Giuseppe Arena , Angelo Magri
发明人： Orazio Battiato , Domenico Repici , Fabrizio Marco Di Paola , Giuseppe Arena , Angelo Magri
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0856 , H01L29/0878 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/66719
摘要： According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.
摘要翻译：根据用于制造MISFET器件的方法的实施例，在半导体晶片中，形成具有第一类型的导电性和第一级掺杂的半导体层。在半导体层中形成有具有与第一类型的导电性相反的第二导电类型的第一体区和第二体区，以及在第一和第二体区之间延伸的富集区。富集区具有第一类导电性和第二级掺杂，高于第一级掺杂。此外，在富集区域和第一和第二体区的一部分之上形成栅电极，并且在栅极电极和半导体层之间形成介电栅极结构，在富集区域上具有较大厚度的电介质栅极结构并且在第一和第二身体区域上具有较小的厚度。为了形成富集区域，在半导体层上形成第一导电层，在第一导电层中形成富集开口，并且通过富集开口将掺杂剂物质引入半导体层。此外，介电栅极结构的形成设想在形成第一体区域和第二体区域之前用电介质材料填充富集开口。

7. 发明申请

US20080169517A1 METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES 有权
标题翻译：用于制造集成在半导体衬底和相应器件中的电子器件的方法
公开(公告)号：US20080169517A1
公开(公告)日：2008-07-17
申请号：US11971113
申请日：2008-01-08
申请人： Ferrucio Frisina , Mario Giuseppe Saggio , Angelo Magri
发明人： Ferrucio Frisina , Mario Giuseppe Saggio , Angelo Magri
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/047 , H01L29/1045 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/6653 , H01L29/7835
摘要： A method for manufacturing electronic devices on a semiconductor substrate with wide band gap that includes the steps of: forming a screening structure on the semiconductor substrate to include at least a dielectric layer that leaves a plurality of areas of the semiconductor substrate exposed, carrying out at least a ion implantation of a first type of dopant in the semiconductor substrate to form at least a first implanted region, carrying out at least a ion implantation of a second type of dopant in the semiconductor substrate to form at least a second implanted region inside the at least a first implanted region, carrying out an activation thermal process of the first type and second type of dopant with low thermal temperature suitable to complete the formation of the at least first and second implanted regions without diffusing the at least first and at least second type dopants in the substrate.
摘要翻译：一种用于在具有宽带隙的半导体衬底上制造电子器件的方法，包括以下步骤：在所述半导体衬底上形成屏蔽结构，以至少包括使所述半导体衬底的多个区域露出的电介质层，至少在所述半导体衬底中的第一类型的掺杂剂的离子注入以形成至少第一注入区域，在所述半导体衬底中至少执行第二类型的掺杂剂的离子注入，以在所述半导体衬底内形成至少第二注入区域至少第一注入区域，其具有适于完成所述至少第一和第二注入区域的形成的第一类型和第二类型掺杂剂的活化热处理，所述第一类型和第二类型的掺杂剂适于完成至少第一和第二注入区域的形成，型掺杂剂。

8. 发明授权

US07304335B2 Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density 有权
标题翻译：具有双重厚度栅极氧化物的垂直导通和平面结构的MOS器件和用于实现具有改善的静态和动态性能以及高缩小密度的功率垂直MOS晶体管的方法
公开(公告)号：US07304335B2
公开(公告)日：2007-12-04
申请号：US11279967
申请日：2006-04-17
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L29/78 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

9. 发明申请

US20070272980A1 Semiconductor device with vertical current flow and low substrate resistance and manufacturing process thereof 有权
标题翻译：具有垂直电流流动和低基板电阻的半导体器件及其制造工艺
公开(公告)号：US20070272980A1
公开(公告)日：2007-11-29
申请号：US11800979
申请日：2007-05-07
申请人： Angelo Magri , Antonio Marino
发明人： Angelo Magri , Antonio Marino
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/743 , H01L23/481 , H01L29/0657 , H01L29/417 , H01L29/41708 , H01L29/41741 , H01L29/41766 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate.
摘要翻译：具有垂直电流的半导体器件包括具有由半导体材料制成的衬底的主体。在身体的第一面上的至少一个电接触。金属化结构形成在主体的与第一面相对的第二面上。金属化结构设置有金属通孔，金属通孔从衬底内的第二面突出，以形成与所述衬底的部分平行的高导电通路。

10. 发明申请

US20060186434A1 VERTICAL-CONDUCTION AND PLANAR-STRUCTURE MOS DEVICE WITH A DOUBLE THICKNESS OF GATE OXIDE AND METHOD FOR REALIZING POWER VERTICAL MOS TRANSISTORS WITH IMPROVED STATIC AND DYNAMIC PERFORMANCE AND HIGH SCALING DOWN DENSITY 有权
标题翻译：具有双重厚度的氧化物的垂直导体和平面结构MOS器件以及用于实现具有改进的静态和动态性能以及高缩放密度的功率垂直MOS晶体管的方法
公开(公告)号：US20060186434A1
公开(公告)日：2006-08-24
申请号：US11279967
申请日：2006-04-17
申请人： Angelo MAGRI' , Ferruccio FRISINA , Giuseppe FERLA , Marco CAMALLERI
发明人： Angelo MAGRI' , Ferruccio FRISINA , Giuseppe FERLA , Marco CAMALLERI
IPC分类号： H01L29/423 , H01L21/332
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

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