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1. 发明授权

US06890806B2 Semiconductor integrated electronic device and corresponding manufacturing method 有权
标题翻译：半导体集成电子器件及相应的制造方法
公开(公告)号：US06890806B2
公开(公告)日：2005-05-10
申请号：US10763626
申请日：2004-01-23
申请人： Gianfranco Cerofolini , Giuseppe Ferla
发明人： Gianfranco Cerofolini , Giuseppe Ferla
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L51/05 , H01L51/30 , H01L51/40 , H01L21/8234
CPC分类号： H01L21/28167 , H01L29/51
摘要： A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.
摘要翻译：公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括在两个硅板之间形成的电介质氧化物层，并且其中硅板全部悬垂在氧化物层周围以限定具有基本上矩形横截面形状的底切。该方法包括以下步骤：将硅板的表面化学改变成在底切中提供的不同的官能团与其余表面中的不同的官能团; 并且将底切中提供的官能团选择性地与具有可逆还原中心和分子长度基本上等于底切宽度的有机分子反应，从而与有机分子的每个末端建立共价键。

2. 发明授权

US4277291A Process for making CMOS field-effect transistors 失效
标题翻译：制造CMOS场效应晶体管的工艺
公开(公告)号：US4277291A
公开(公告)日：1981-07-07
申请号：US113594
申请日：1980-01-21
申请人： Gianfranco Cerofolini , Giuseppe Ferla
发明人： Gianfranco Cerofolini , Giuseppe Ferla
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/06
CPC分类号： H01L29/0638 , H01L21/76218 , H01L21/823878 , Y10S148/07
摘要： Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a photoresist mask (14), leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low energy level to penetrate the last-mentioned oxide portion and then at a higher energy level with additional penetration of the second patch (10b) to form a p-well (18) bounded by a p+ guard zone (20); the previously implanted arsenic ions in the unbombarded area form an n+ guard zone (22). Next, the wafer is subjected to a heat treatment in an oxidizing atmosphere with resulting deepening of the guard zones and the p-well and with growth of the oxide layer especially in areas not overlain by the patches whose subsequent removal, together with other oxide portions except for a residue forming two insulating gate supports (24a, 24b), exposes source and drain areas of the p-well (18) and of an n-type pedestal (19) separated therefrom by the guard zones (20, 22). A phosphorus-doped oxide layer (28) is then formed above the p-well whereupon the wafer is heated in a boron atmosphere.
摘要翻译：在小厚度的上覆氧化物层（8）上的n型衬底（2）的间隔开的区域之上形成两块氮化硅。然后通过氧化物层将砷离子注入到未被贴片覆盖的衬底区域中，然后通过光致抗蚀剂掩模（14）覆盖一个贴片（10a）和氧化物层的相邻部分，留下未受保护的第二贴片（10b）和与其相邻的氧化物部分。然后用硼离子轰击晶片，首先在较低的能量水平上穿透最后提及的氧化物部分，然后在较高能量水平，另外穿透第二贴片（10b）以形成p阱（18）由p +保护区（20）限定; 未轰炸区域中的先前注入的砷离子形成n +保护区（22）。接下来，在氧化气氛中对晶片进行热处理，导致保护区和p阱的加深，并且随着氧化物层的生长，特别是在不被其后除去的贴片的区域中，以及其它氧化物部分除了形成两个绝缘栅极支撑件（24a，24b）的残余物之外，露出p阱（18）的源极和漏极区域以及由保护区域（20,22）与其分离的n型基座（19）。然后在p阱上形成磷掺杂氧化物层（28），随后在硼气氛中加热晶片。

3. 发明授权

US06724009B2 Semiconductor integrated electronic device and corresponding manufacturing method 有权
标题翻译：半导体集成电子器件及相应的制造方法
公开(公告)号：US06724009B2
公开(公告)日：2004-04-20
申请号：US10199964
申请日：2002-07-18
申请人： Gianfranco Cerofolini , Giuseppe Ferla
发明人： Gianfranco Cerofolini , Giuseppe Ferla
IPC分类号： H01L3524
CPC分类号： H01L21/28167 , H01L29/51
摘要： A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.
摘要翻译：公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括在两个硅板之间形成的电介质氧化物层，并且其中硅板全部悬垂在氧化物层周围以限定具有基本上矩形横截面形状的底切。该方法包括以下步骤：将硅板的表面化学改变成在底切中提供的不同的官能团与其余表面中的不同的官能团; 并且将底切中提供的官能团选择性地与具有可逆还原中心和分子长度基本上等于底切宽度的有机分子反应，从而与有机分子的每个末端建立共价键。

4. 发明申请

US20110081759A1 POWER MOS ELECTRONIC DEVICE AND CORRESPONDING REALIZING METHOD 有权
公开(公告)号：US20110081759A1
公开(公告)日：2011-04-07
申请号：US12967845
申请日：2010-12-14
申请人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L21/8232
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

5. 发明申请

US20090321826A1 METHOD FOR MANUFACTURING A HIGH INTEGRATION DENSITY POWER MOS DEVICE 有权
标题翻译：用于制造高集成度密度功率MOS器件的方法
公开(公告)号：US20090321826A1
公开(公告)日：2009-12-31
申请号：US12551999
申请日：2009-09-01
申请人： Giuseppe ARENA , Giuseppe Ferla , Marco Camalleri
发明人： Giuseppe ARENA , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/2815 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/4933 , H01L29/66712
摘要： A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.
摘要翻译：用于实现高集成度功率MOS器件的方法包括以下步骤：提供具有第一类型导电性的掺杂半导体衬底; 在所述基板上形成具有较低导电率的半导体层; 在半导体层上形成厚度介于3000和13000A（埃）之间的介电层; 在电介质层上沉积硬掩模层; 通过掩模层掩蔽硬掩模层; 蚀刻硬掩模层和下面的介电层以限定多个硬掩模部分以保护所述介电层; 去除掩蔽层; 各向同性和横向蚀刻所述介电层，在所述硬掩模部分下面的所述介电层中形成横向空腔; 形成厚度为150至1500A（埃）的栅极氧化物，其在所述空腔中沉积导体材料并且在其上方，以形成与包括所述厚介电层和所述栅极氧化物的栅极结构完全对准的凹陷间隔物。

6. 发明授权

US07569883B2 Switching-controlled power MOS electronic device 有权
标题翻译：开关控制功率MOS电子器件
公开(公告)号：US07569883B2
公开(公告)日：2009-08-04
申请号：US11285759
申请日：2005-11-21
申请人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Giuseppe Grimaldi , Gaetano Bazzano
发明人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Giuseppe Grimaldi , Gaetano Bazzano
IPC分类号： H01L29/76 , H01L29/94 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
摘要翻译：这种类型的功率电子MOS器件包括多个基本功率MOS晶体管和一个栅极结构，该栅极结构包括由第一导电材料（例如多晶硅），多个栅极指状物或连接到栅极焊盘的金属轨道至少一个与至少一个所述导电带串联布置的连接层。这种门结构包括形成在导电条的上表面上并适当地形成在连接层上的至少多个独立的岛。所述岛通过至少一种第二导电材料如硅化物实现。

7. 发明授权

US06642121B2 Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition 有权
公开(公告)号：US06642121B2
公开(公告)日：2003-11-04
申请号：US10032334
申请日：2001-12-18
申请人： Cateno M. Camalleri , Simona Lorenti , Denise Cali′ , Patrizia Vasquez , Giuseppe Ferla
发明人： Cateno M. Camalleri , Simona Lorenti , Denise Cali′ , Patrizia Vasquez , Giuseppe Ferla
IPC分类号： H01L218222
CPC分类号： H01L29/66272 , H01L21/2256 , H01L29/7311
摘要： A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.1 and 120 minutes.

8. 发明授权

US06468866B2 Single feature size MOS technology power device 有权
标题翻译：单功能尺寸MOS技术电源设备
公开(公告)号：US06468866B2
公开(公告)日：2002-10-22
申请号：US09427237
申请日：1999-10-26
申请人： Ferruccio Frisina , Angelo Magri , Giuseppe Ferla , Richard A. Blanchard
发明人： Ferruccio Frisina , Angelo Magri , Giuseppe Ferla , Richard A. Blanchard
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/66333
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.
摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，覆盖半导体材料层的导电绝缘栅极层和多个基本功能单元。导电绝缘栅层包括置于半导体材料层上方的第一绝缘材料层，位于第一绝缘材料层上方的导电材料层和置于导电材料层上方的第二绝缘材料层。每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。每个基本功能单元还包括在细长体区域上方延伸的绝缘栅极层中的细长窗口。每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括多个绝缘材料侧壁间隔物，其沿着每个细长窗口的细长边缘设置在半导体材料层之上，以密封绝缘栅极层中每个细长窗口的边缘与设置在绝缘栅极上的源极金属层层和半导体材料层。源极金属层沿着细长主体区域的长度通过每个细长窗口接触每个体区域和每个源极区域。

9. 发明授权

US6064087A Single feature size MOS technology power device 失效
公开(公告)号：US6064087A
公开(公告)日：2000-05-16
申请号：US739466
申请日：1996-10-29
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L29/74 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L29/0847
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

10. 发明授权

US5841167A MOS-technology power device integrated structure 失效
公开(公告)号：US5841167A
公开(公告)日：1998-11-24
申请号：US772657
申请日：1996-12-23
申请人： Antonio Grimaldi , Antonino Schillaci , Ferruccio Frisina , Giuseppe Ferla
发明人： Antonio Grimaldi , Antonino Schillaci , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L21/336 , H01L23/482 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66712 , H01L23/4824 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7802 , H01L29/41725 , H01L2924/0002
摘要： A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of bodystripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion. The body stripes are divided by the at least one first elongated stripe into at least two groups of body stripes, wherein one end of each body stripe is merged with the annular frame portion of the second conductivity type and the other end is merged with the at least one first elongated stripe. A conductive gate finger is insulatively disposed above the first elongated stripe and is part of the first web structure. A conductive gate ring surrounds the conductive gate layer and the conductive gate finger and completes the first web structure. A metal gate finger is disposed above the conductive gate finger and is merged at its ends with a metal gate ring structure disposed above the conductive gate ring to provide a third web structure. Source metal plates cover the at least two groups of body stripes and contact each source region and each body stripe to form a source electrode of the power device. A bottom surface of the semiconductor material layer forms a drain of the power device.

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