专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070174589A1 Processor having inactive state of operation and method thereof 有权
标题翻译：具有无效操作状态的处理器及其方法
公开(公告)号：US20070174589A1
公开(公告)日：2007-07-26
申请号：US11319805
申请日：2005-12-29
申请人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
发明人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种具有非活动状态的处理器及其方法。根据本发明的一些演示实施例的处理器，处理器可以包括用于确定要进入的不活动状态的控制器，并且使一个或多个执行单元的预定集合执行预定的一个或多个进入非活动状态之前的更多微操作。描述和要求保护其他实施例。

2. 发明授权

US07536485B2 Processor having inactive state of operation and method thereof 有权
标题翻译：具有无效操作状态的处理器及其方法
公开(公告)号：US07536485B2
公开(公告)日：2009-05-19
申请号：US11319805
申请日：2005-12-29
申请人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
发明人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
IPC分类号： G06F13/10 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种具有非活动状态的处理器及其方法。根据本发明的一些演示实施例的处理器，处理器可以包括用于确定要进入的不活动状态的控制器，并且使一个或多个执行单元的预定集合执行预定的一个或多个进入非活动状态之前的更多微操作。描述和要求保护其他实施例。

3. 发明申请

US20140089942A1 SYSTEM TO PROFILE AND OPTIMIZE USER SOFTWARE IN A MANAGED RUN-TIME ENVIRONMENT 审中-公开
标题翻译：在管理的运行环境中配置和优化用户软件的系统
公开(公告)号：US20140089942A1
公开(公告)日：2014-03-27
申请号：US14036768
申请日：2013-09-25
申请人： Chris J. Newburn , Robert P. Knight , Robert Y. Geva , Dion Rodgers , Xiang Zou , Hong Wang , Bryant E. Bigbee , Ittai Anati
发明人： Chris J. Newburn , Robert P. Knight , Robert Y. Geva , Dion Rodgers , Xiang Zou , Hong Wang , Bryant E. Bigbee , Ittai Anati
IPC分类号： G06F9/54
CPC分类号： G06F9/542 , G06F11/348 , G06F11/3612 , G06F2201/86 , G06F2201/885
摘要： Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.
摘要翻译：用于监控处理资源内的性能的方法，装置和系统，其可用于修改用户级软件。本发明的一些实施例涉及允许用户实时地在每个线程的基础上改进在处理资源上运行的软件并且不产生显着的处理开销的架构。

4. 发明授权

US08631261B2 Context state management for processor feature sets 有权
公开(公告)号：US08631261B2
公开(公告)日：2014-01-14
申请号：US11967303
申请日：2007-12-31
申请人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
发明人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
IPC分类号： G06F1/32 , G06F9/44
CPC分类号： G06F9/30043 , G06F9/30003 , G06F9/30101 , G06F9/461
摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

5. 发明授权

US08301868B2 System to profile and optimize user software in a managed run-time environment 失效
标题翻译：系统在受管理的运行时环境中配置和优化用户软件
公开(公告)号：US08301868B2
公开(公告)日：2012-10-30
申请号：US11233741
申请日：2005-09-23
申请人： Chris J. Newburn , Robert Knight , Robert Geva , Dion Rodgers , Xiang Zou , Hong Wang , Bryant E. Bigbee , Ittai Anati
发明人： Chris J. Newburn , Robert Knight , Robert Geva , Dion Rodgers , Xiang Zou , Hong Wang , Bryant E. Bigbee , Ittai Anati
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/542 , G06F11/348 , G06F11/3612 , G06F2201/86 , G06F2201/885
摘要： Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.
摘要翻译：用于监控处理资源内的性能的方法，装置和系统，其可用于修改用户级软件。本发明的一些实施例涉及允许用户实时地在每个线程的基础上改进在处理资源上运行的软件并且不产生显着的处理开销的架构。

6. 发明授权

US07430656B2 System and method of converting data formats and communicating between execution units 有权
标题翻译：转换数据格式和执行单元之间的通信的系统和方法
公开(公告)号：US07430656B2
公开(公告)日：2008-09-30
申请号：US10334114
申请日：2002-12-31
申请人： Zeev Sperber , Ittai Anati , Oded Liron , Mohammad Abdallah
发明人： Zeev Sperber , Ittai Anati , Oded Liron , Mohammad Abdallah
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F7/00
CPC分类号： G06F9/30014 , G06F9/226 , G06F9/30025 , G06F9/30036 , G06F9/3017 , G06F9/3824 , G06F9/3826 , G06F9/3861
摘要： A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.
摘要翻译：一种方法和系统，包括以多类型指令集体系结构中的执行单元之间的架构格式发送数据，并且以结构格式将接收的数据转换为内部格式，并以内部格式输出的数据基于操作代码和微指令的数据类型。

7. 发明申请

US20070150705A1 Efficient counting for iterative instructions 审中-公开
标题翻译：有效计数迭代指令
公开(公告)号：US20070150705A1
公开(公告)日：2007-06-28
申请号：US11320262
申请日：2005-12-28
申请人： Michael Mishaeli , Ittai Anati
发明人： Michael Mishaeli , Ittai Anati
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/325 , G06F9/3857 , G06F9/3861
摘要： Methods and apparatus to provide efficient counting of the number of retired iterations of an iterative instruction are described. In one embodiment, the number of retired iterations of an iterative instruction is determined.
摘要翻译：描述了提供迭代指令的退出迭代次数的有效计数的方法和装置。在一个实施例中，确定迭代指令的退出迭代次数。

8. 发明申请

US20070038844A1 Technique to combine instructions 有权
标题翻译：技术结合说明
公开(公告)号：US20070038844A1
公开(公告)日：2007-02-15
申请号：US11200777
申请日：2005-08-09
申请人： Robert Valentine , Ittai Anati , Zeev Sperber , Ido Oziel , Gregory Pribush , Amir Leibovitz
发明人： Robert Valentine , Ittai Anati , Zeev Sperber , Ido Oziel , Gregory Pribush , Amir Leibovitz
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3863
摘要： A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.
摘要翻译：微操作（uop）融合技术。更具体地说，本发明的实施例涉及一种融合来自两个或更多个指令的两个或更多个uop的技术。

9. 发明申请

US20050060524A1 Processor and methods for micro-operations generation 审中-公开
标题翻译：用于微操作生成的处理器和方法
公开(公告)号：US20050060524A1
公开(公告)日：2005-03-17
申请号：US10663832
申请日：2003-09-17
申请人： Ittai Anati , Gregory Pribush
发明人： Ittai Anati , Gregory Pribush
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/44
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3853
摘要： A processor includes an instruction decoder to decode instructions into micro-operations for execution. The instruction decoder may include a programmable logic array to store templates to be addressed by instructions during decoding of the instructions. A collapsed template is addressed by one or more instructions during decoding into fused micro-operations and by one or more instructions during decoding into simple micro-operations. The instruction decoder may also include a multiplexer to select values of a field of the micro-operation based at least on an indication that the instruction being decoded is not being decoded into a simple micro-operation. The instruction decoder may also include a multiplexer to select values of a field of the micro-operation based at least on bits of a template field, where the number of bits of the template field is less than the number of bits of the field of the micro-operation.
摘要翻译：处理器包括用于将指令解码成用于执行的微操作的指令解码器。指令解码器可以包括可编程逻辑阵列，以在解码指令期间存储要由指令寻址的模板。在解码成融合的微操作期间，通过一个或多个指令，在解码成简单的微操作期间，通过一个或多个指令来解决折叠的模板。指令解码器还可以包括多路复用器，至少基于正被解码的指令未被解码为简单的微操作的指示来选择微操作的场的值。指令解码器还可以包括多路复用器，用于基于模板字段的至少一个比特来选择微操作的字段的值，其中模板字段的比特数小于该字段的比特数微操作。

10. 发明申请

US20160117265A1 MAINTAINING A SECURE PROCESSING ENVIRONMENT ACROSS POWER CYCLES 有权
标题翻译：维护安全循环的安全环境
公开(公告)号：US20160117265A1
公开(公告)日：2016-04-28
申请号：US14525421
申请日：2014-10-28
申请人： Francis X. MCKEEN , Vincent Scarlata , Carlos Rozas , Ittai Anati , Vedvyas Shanbhogue
发明人： Francis X. MCKEEN , Vincent Scarlata , Carlos Rozas , Ittai Anati , Vedvyas Shanbhogue
IPC分类号： G06F12/14 , G06F12/08
CPC分类号： G06F12/1416 , G06F9/4418 , G06F12/0804 , G06F12/0875 , G06F12/1408 , G06F12/1441 , G06F21/53 , G06F2212/1016 , G06F2212/1028 , G06F2212/1052 , G06F2212/152 , G06F2212/452 , Y02D10/13
摘要： Embodiments of an invention for maintaining a secure processing environment across power cycles are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to evict a root version array page entry from a secure cache. The execution unit is to execute the instruction. Execution of the instruction includes generating a blob to contain information to maintain a secure processing environment across a power cycle and storing the blob in a non-volatile memory.
摘要翻译：公开了用于在电力周期内保持安全处理环境的发明的实施例。在一个实施例中，处理器包括指令单元和执行单元。指令单元接收从安全缓存驱逐根版本阵列页条目的指令。执行单元执行指令。该指令的执行包括生成一个blob以包含信息以在整个电源周期内维护一个安全的处理环境，并将该blob存储在一个非易失性存储器中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式